Line Coverage for Module :
spi_cmdparse
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 108 | 108 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| ALWAYS | 90 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| ALWAYS | 185 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 196 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 198 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 202 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 204 | 1 | 1 | 100.00 |
| ALWAYS | 208 | 4 | 4 | 100.00 |
| ALWAYS | 218 | 6 | 6 | 100.00 |
| ALWAYS | 233 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 253 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 254 | 1 | 1 | 100.00 |
| ALWAYS | 263 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
| ALWAYS | 283 | 11 | 11 | 100.00 |
| CONT_ASSIGN | 295 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 302 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 303 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 304 | 1 | 1 | 100.00 |
| ALWAYS | 307 | 4 | 4 | 100.00 |
| ALWAYS | 315 | 48 | 48 | 100.00 |
84 assign cmd_config_req_o = 1'b 0;
85 1/1 assign cmd_config_idx_o = data_i[4:0];
Tests: T1 T2 T3
86
87 // Only opcode in the cmd_info is used. Tie the rest of the members.
88 logic unused_cmdinfo_members;
89 always_comb begin
90 1/1 unused_cmdinfo_members = 1'b 0;
Tests: T1 T2 T3
91 1/1 for (int unsigned i = 0 ; i < NumTotalCmdInfo ; i++) begin
Tests: T1 T2 T3
92 1/1 unused_cmdinfo_members ^= ^{ cmd_info_i[i].addr_mode,
Tests: T1 T2 T3
93 cmd_info_i[i].addr_swap_en,
94 cmd_info_i[i].dummy_en,
95 ^cmd_info_i[i].dummy_size,
96 cmd_info_i[i].payload_dir,
97 ^cmd_info_i[i].payload_en,
98 cmd_info_i[i].payload_swap_en};
99 end
100 end
101
102 ////////////////
103 // Definition //
104 ////////////////
105 typedef enum logic [3:0] {
106 // At Idle, FSM waits command valid signal.
107 // The last 8th bit in the command byte determines the last two bit from
108 // `upload_mask`. Then triggers proper downstream modules based on
109 // predefined opcode and `upload_mask`.
110 StIdle,
111
112 // State machine has state for each downstream module, to track and select
113 // proper io_mode and signals
114 StStatus,
115 StSfdp,
116 StJedec,
117
118 // Mailbox is processed in Read Command block.
119 StReadCmd,
120
121 StUpload,
122
123 // EN4B/ EX4B fall into this state
124 StAddr4B,
125
126 // Write Enable / Disable state
127 StWrEn,
128
129 // If opcode does not matched, FSM moves to here and wait the reset.
130 StWait
131 } st_e;
132 st_e st, st_d;
133
134 // spi_flash_cmd_e defines HW supported (TBD for IO) commands.
135 // If received SPI Flash command falls into one of these commands, the module
136 // processes the command without SW intervention.
137 typedef enum logic [7:0] {
138 OpReadStatus1 = 'h 05,
139 OpReadStatus2 = 'h 35,
140 OpReadStatus3 = 'h 15,
141 OpReadJEDEC = 'h 9F,
142 OpReadSfdp = 'h 5A,
143 OpReadNormal = 'h 03,
144 OpReadFast = 'h 0B,
145 OpReadDual = 'h 3B,
146 OpReadQuad = 'h 6B,
147 // Supporting DualIO/ QuadIO is TBD.
148 OpReadDualIO = 'h BB,
149 OpReadQuadIO = 'h EB
150 } spi_flash_cmd_e;
151
152 ////////////
153 // Signal //
154 ////////////
155 sel_datapath_e sel_dp;
156 1/1 assign sel_dp_o = sel_dp;
Tests: T1 T2 T3
157 `ASSERT_KNOWN(SelDpKnown_A, sel_dp_o)
158
159 sel_datapath_e cmd_only_sel_dp;
160 1/1 assign cmd_only_sel_dp_o = cmd_only_sel_dp;
Tests: T1 T2 T3
161 `ASSERT_KNOWN(CmdOnlySelDpKnown_A, cmd_only_sel_dp_o)
162
163 // FSM asserts latching enable signal for cmd_info in 8th opcode cycle.
164 logic latch_cmdinfo;
165 cmd_info_t cmd_info_d, cmd_info_q;
166 logic [CmdInfoIdxW-1:0] cmd_info_idx_d, cmd_info_idx_q;
167
168 // the logic operates only when module_active condition is met
169 logic module_active;
170 logic in_flashmode, in_passthrough;
171
172 // Intercept passthrough if Passthrough is in active
173 // As intercept does not affect in Flash mode, the logic ignores
174 // `in_passthrough` condition.
175 logic intercept_d;
176
177 // below signals are used in the FSM to determine to activate a certain
178 // datapath based on the received input (opcode). The opcode is the SW
179 // configurable CSRs `cmd_info_i`.
180 logic opcode_readstatus, opcode_readjedec, opcode_readsfdp, opcode_readcmd;
181 logic opcode_en4b, opcode_ex4b;
182 logic opcode_wren, opcode_wrdi;
183
184 always_comb begin
185 1/1 opcode_readstatus = 1'b 0;
Tests: T1 T2 T3
186 1/1 for (int i = 0 ; i < 3 ; i++) begin
Tests: T1 T2 T3
187 1/1 if (cmd_info_i[CmdInfoReadStatus1+i].valid
Tests: T1 T2 T3
188 && (data_i == cmd_info_i[CmdInfoReadStatus1+i].opcode)) begin
189 1/1 opcode_readstatus = 1'b 1;
Tests: T6 T7 T8
190 end
MISSING_ELSE
191 end
192 end
193
194 1/1 assign opcode_readjedec = cmd_info_i[CmdInfoReadJedecId].valid
Tests: T1 T2 T3
195 && (data_i == cmd_info_i[CmdInfoReadJedecId].opcode);
196 1/1 assign opcode_readsfdp = cmd_info_i[CmdInfoReadSfdp].valid
Tests: T1 T2 T3
197 && (data_i == cmd_info_i[CmdInfoReadSfdp].opcode);
198 1/1 assign opcode_en4b = !sck_status_busy_i && cmd_info_i[CmdInfoEn4B].valid
Tests: T1 T2 T3
199 && (data_i == cmd_info_i[CmdInfoEn4B].opcode);
200 1/1 assign opcode_ex4b = !sck_status_busy_i && cmd_info_i[CmdInfoEx4B].valid
Tests: T1 T2 T3
201 && (data_i == cmd_info_i[CmdInfoEx4B].opcode);
202 1/1 assign opcode_wren = !sck_status_busy_i && cmd_info_i[CmdInfoWrEn].valid
Tests: T1 T2 T3
203 && (data_i == cmd_info_i[CmdInfoWrEn].opcode);
204 1/1 assign opcode_wrdi = !sck_status_busy_i && cmd_info_i[CmdInfoWrDi].valid
Tests: T1 T2 T3
205 && (data_i == cmd_info_i[CmdInfoWrDi].opcode);
206
207 always_comb begin
208 1/1 opcode_readcmd = 1'b 0;
Tests: T1 T2 T3
209 1/1 for (int unsigned i = CmdInfoReadCmdStart ; i <= CmdInfoReadCmdEnd ; i++) begin
Tests: T1 T2 T3
210 1/1 if (cmd_info_i[i].valid && data_i == cmd_info_i[i].opcode) begin
Tests: T1 T2 T3
211 1/1 opcode_readcmd = 1'b 1;
Tests: T6 T7 T8
212 end
MISSING_ELSE
213 end
214 end
215
216 // cmd_info latch
217 always_ff @(posedge clk_i or negedge rst_ni) begin
218 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
219 1/1 cmd_info_q <= '{
Tests: T1 T2 T3
220 payload_dir: payload_dir_e'(PayloadIn),
221 addr_mode: addr_mode_e'(0),
222 read_pipeline_mode: read_pipeline_mode_e'(0),
223 default: '0
224 };
225 1/1 cmd_info_idx_q <= '0;
Tests: T1 T2 T3
226 1/1 end else if (latch_cmdinfo) begin
Tests: T6 T7 T8
227 1/1 cmd_info_q <= cmd_info_d;
Tests: T6 T7 T8
228 1/1 cmd_info_idx_q <= cmd_info_idx_d;
Tests: T6 T7 T8
229 end
MISSING_ELSE
230 end
231
232 always_comb begin
233 1/1 cmd_info_d = '{
Tests: T1 T2 T3
234 payload_dir: payload_dir_e'(PayloadIn),
235 addr_mode: addr_mode_e'(0),
236 read_pipeline_mode: read_pipeline_mode_e'(0),
237 default: '0
238 };
239 1/1 cmd_info_idx_d = '0;
Tests: T1 T2 T3
240 1/1 if ((st == StIdle) && module_active && data_valid_i) begin
Tests: T1 T2 T3
241 1/1 for (int unsigned i = 0 ; i < NumTotalCmdInfo ; i++ ) begin
Tests: T1 T2 T3
242 1/1 if (cmd_info_i[i].valid && (data_i == cmd_info_i[i].opcode)) begin
Tests: T1 T2 T3
243 1/1 cmd_info_d = cmd_info_i[i];
Tests: T6 T7 T8
244 1/1 cmd_info_idx_d = CmdInfoIdxW'(i);
Tests: T6 T7 T8
245 end
MISSING_ELSE
246 end
247 end
MISSING_ELSE
248 end
249
250 // cmd_info & cmd_info_idx are registered output in the cmdparse module.
251 // The upload module in SPI_DEVICE uses cmd_info to determine if the address
252 // field exists or not.
253 1/1 assign cmd_info_o = cmd_info_q;
Tests: T1 T2 T3
254 1/1 assign cmd_info_idx_o = cmd_info_idx_q;
Tests: T1 T2 T3
255
256 // The cmd_info value arrives to the rest of the module one clock late. It
257 // results in the upload module to assume the command does not have the
258 // address field.
259
260 // This commit pulls in the cmd_info one clock early. It leads to longer
261 // datapath as cmdparse cannot register the data.
262 always_comb begin : cmd_only_info_output
263 1/1 cmd_only_info_o = '{
Tests: T1 T2 T3
264 payload_dir: payload_dir_e'(PayloadIn),
265 addr_mode: addr_mode_e'(0),
266 read_pipeline_mode: read_pipeline_mode_e'(0),
267 default: '0
268 };
269 1/1 cmd_only_info_idx_o = '0;
Tests: T1 T2 T3
270
271 1/1 if ((st == StIdle) && module_active && data_valid_i) begin
Tests: T1 T2 T3
272 1/1 cmd_only_info_o = cmd_info_d;
Tests: T1 T2 T3
273 1/1 cmd_only_info_idx_o = cmd_info_idx_d;
Tests: T1 T2 T3
274 end
MISSING_ELSE
275 end
276
277 // Check upload field in the cmd_info
278 logic upload;
279 1/1 assign upload = cmd_info_d.upload && !sck_status_busy_i;
Tests: T1 T2 T3
280
281 // Intercept: Latched in SCK
282 always_ff @(posedge clk_i or negedge rst_ni) begin
283 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
284 1/1 intercept_status_o <= 1'b 0;
Tests: T1 T2 T3
285 1/1 intercept_jedec_o <= 1'b 0;
Tests: T1 T2 T3
286 1/1 intercept_sfdp_o <= 1'b 0;
Tests: T1 T2 T3
287 1/1 end else if (intercept_d) begin
Tests: T6 T7 T8
288 2/2 if (opcode_readstatus) intercept_status_o <= 1'b 1;
Tests: T9 T55 T60 | T9 T55 T60
MISSING_ELSE
289 2/2 if (opcode_readjedec) intercept_jedec_o <= 1'b 1;
Tests: T9 T55 T60 | T45 T51 T66
MISSING_ELSE
290 2/2 if (opcode_readsfdp) intercept_sfdp_o <= 1'b 1;
Tests: T9 T55 T60 | T45 T51 T52
MISSING_ELSE
291 end
MISSING_ELSE
292 end
293
294 // CFG: Added 2-stage pipeline for read payloads
295 1/1 assign cmd_read_pipeline_sel_o = (cmd_info_q.read_pipeline_mode == RdPipeTwoStageHalfCycle) ||
Tests: T1 T2 T3
296 (cmd_info_q.read_pipeline_mode == RdPipeTwoStageFullCycle);
297
298 ///////////////////
299 // State Machine //
300 ///////////////////
301
302 1/1 assign in_flashmode = spi_mode_i == FlashMode ;
Tests: T1 T2 T3
303 1/1 assign in_passthrough = spi_mode_i == PassThrough ;
Tests: T1 T2 T3
304 1/1 assign module_active = in_flashmode || in_passthrough ;
Tests: T1 T2 T3
305
306 always_ff @(posedge clk_i or negedge rst_ni) begin
307 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
308 1/1 st <= StIdle;
Tests: T1 T2 T3
309 1/1 end else if (module_active) begin
Tests: T6 T7 T8
310 1/1 st <= st_d;
Tests: T6 T7 T8
311 end
==> MISSING_ELSE
312 end
313
314 always_comb begin
315 1/1 st_d = st;
Tests: T1 T2 T3
316
317 1/1 sel_dp = DpNone;
Tests: T1 T2 T3
318 1/1 cmd_only_sel_dp = DpNone;
Tests: T1 T2 T3
319
320 1/1 cmd_sync_pulse_o = 1'b0;
Tests: T1 T2 T3
321 1/1 latch_cmdinfo = 1'b 0;
Tests: T1 T2 T3
322
323 1/1 intercept_d = 1'b 0;
Tests: T1 T2 T3
324
325 1/1 unique case (st)
Tests: T1 T2 T3
326 StIdle: begin
327 1/1 if (module_active && data_valid_i && cmd_info_d.valid) begin
Tests: T1 T2 T3
328 // 8th bit is valid here
329 1/1 latch_cmdinfo = 1'b 1;
Tests: T6 T7 T8
330 1/1 cmd_sync_pulse_o = 1'b1;
Tests: T6 T7 T8
331
332 1/1 priority case (1'b 1)
Tests: T6 T7 T8
333 opcode_readstatus: begin
334 1/1 if (in_flashmode) begin
Tests: T6 T9 T17
335 1/1 st_d = StStatus;
Tests: T53 T43 T54
336 1/1 end else if (cfg_intercept_en_status_i) begin
Tests: T6 T9 T17
337 1/1 st_d = StStatus;
Tests: T9 T55 T60
338 1/1 intercept_d = 1'b 1;
Tests: T9 T55 T60
339 end else begin
340 1/1 st_d = StWait;
Tests: T6 T17 T18
341 end
342 end
343
344 opcode_readjedec: begin
345 1/1 if (in_flashmode) begin
Tests: T6 T10 T39
346 1/1 st_d = StJedec;
Tests: T53 T43 T54
347 1/1 end else if (cfg_intercept_en_jedec_i) begin
Tests: T6 T10 T39
348 1/1 st_d = StJedec;
Tests: T45 T51 T66
349 1/1 intercept_d = 1'b 1;
Tests: T45 T51 T66
350 end else begin
351 1/1 st_d = StWait;
Tests: T6 T10 T39
352 end
353 end
354
355 // Read SFDP may combine with Read command later
356 opcode_readsfdp: begin
357 1/1 if (in_flashmode) begin
Tests: T10 T53 T56
358 1/1 st_d = StSfdp;
Tests: T53 T43 T54
359 1/1 end else if (cfg_intercept_en_sfdp_i) begin
Tests: T10 T56 T45
360 1/1 st_d = StSfdp;
Tests: T45 T51 T52
361 1/1 intercept_d = 1'b 1;
Tests: T45 T51 T52
362 end else begin
363 // Check passthrough
364 1/1 st_d = StWait;
Tests: T10 T56 T50
365 end
366 end
367
368 opcode_readcmd: begin
369 // Let it move to ReadCmd regardless of the modes
370 // Then, ReadCmd will handle Mailbox command if received address
371 // falls into Mailbox address range
372 1/1 st_d = StReadCmd;
Tests: T6 T7 T8
373 end
374
375 upload: begin
376 1/1 st_d = StUpload;
Tests: T43 T45 T54
377 1/1 cmd_only_sel_dp = DpUpload;
Tests: T43 T45 T54
378 end
379
380 opcode_en4b, opcode_ex4b: begin
381 1/1 st_d = StAddr4B;
Tests: T53 T57 T55
382
383 // opcode only commands. Need to assert DP before transition
384 1/1 cmd_only_sel_dp = (opcode_en4b) ? DpEn4B : DpEx4B ;
Tests: T53 T57 T55
385 end
386
387 opcode_wren, opcode_wrdi: begin
388 1/1 st_d = StWrEn;
Tests: T13 T53 T57
389
390 // opcode only commands. Need to assert DP before transition
391 1/1 cmd_only_sel_dp = (opcode_wren) ? DpWrEn : DpWrDi ;
Tests: T13 T53 T57
392 end
393
394 default: begin
395 st_d = StWait;
396
397 // DpNone
398 end
399 endcase
400 end // if (module_active && data_valid_i && cmd_info_d.valid)
401 1/1 else if (module_active && data_valid_i) begin
Tests: T1 T2 T3
402 // Could not find valid command information entry.
403 1/1 st_d = StWait;
Tests: T1 T2 T3
404 1/1 cmd_sync_pulse_o = 1'b1;
Tests: T1 T2 T3
405 end // if (module_active && data_valid_i)
MISSING_ELSE
406 end
407
408 // dead-end states below. Reset (CSb de-assertion) let SM back to Idle
409 1/1 StStatus: sel_dp = DpReadStatus;
Tests: T9 T53 T55
410
411 1/1 StJedec: sel_dp = DpReadJEDEC;
Tests: T53 T43 T45
412
413 1/1 StSfdp: sel_dp = DpReadSFDP;
Tests: T53 T43 T45
414
415 1/1 StReadCmd: sel_dp = DpReadCmd;
Tests: T6 T7 T8
416
417 1/1 StUpload: sel_dp = DpUpload;
Tests: T43 T45 T54
418
419 1/1 StAddr4B: sel_dp = DpNone; // Terminal state wait reset
Tests: T53 T57 T55
420
421 1/1 StWrEn: sel_dp = DpNone; // Terminal state wait reset
Tests: T13 T53 T57
422
423 StWait: begin
424 1/1 st_d = StWait;
Tests: T6 T7 T8
425
426 1/1 sel_dp = DpNone;
Tests: T6 T7 T8
427 end
428
429 default: begin
430 sel_dp = DpNone;
431
432 st_d = StIdle;
Cond Coverage for Module :
spi_cmdparse
| Total | Covered | Percent |
|---|
| Conditions | 89 | 83 | 93.26 |
| Logical | 89 | 83 | 93.26 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 187
EXPRESSION (cmd_info_i[(CmdInfoReadStatus1 + i)].valid && (data_i == cmd_info_i[(CmdInfoReadStatus1 + i)].opcode))
---------------------1-------------------- ---------------------------2---------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T6,T7,T8 |
| 1 | 1 | Covered | T6,T7,T8 |
LINE 187
SUB-EXPRESSION (data_i == cmd_info_i[(CmdInfoReadStatus1 + i)].opcode)
---------------------------1---------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T5,T6 |
LINE 194
EXPRESSION (cmd_info_i[CmdInfoReadJedecId].valid && (data_i == cmd_info_i[CmdInfoReadJedecId].opcode))
------------------1----------------- ------------------------2------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T7 |
| 1 | 0 | Covered | T6,T9,T10 |
| 1 | 1 | Covered | T6,T9,T10 |
LINE 194
SUB-EXPRESSION (data_i == cmd_info_i[CmdInfoReadJedecId].opcode)
------------------------1------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T5,T6 |
LINE 196
EXPRESSION (cmd_info_i[CmdInfoReadSfdp].valid && (data_i == cmd_info_i[CmdInfoReadSfdp].opcode))
----------------1---------------- -----------------------2----------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T9,T10,T12 |
| 1 | 1 | Covered | T9,T10,T12 |
LINE 196
SUB-EXPRESSION (data_i == cmd_info_i[CmdInfoReadSfdp].opcode)
-----------------------1----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T5,T6 |
LINE 198
EXPRESSION (((!sck_status_busy_i)) && cmd_info_i[CmdInfoEn4B].valid && (data_i == cmd_info_i[CmdInfoEn4B].opcode))
-----------1---------- --------------2-------------- ---------------------3--------------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T43,T45,T54 |
| 1 | 0 | 1 | Covered | T4,T5,T6 |
| 1 | 1 | 0 | Covered | T38,T53,T57 |
| 1 | 1 | 1 | Covered | T38,T53,T57 |
LINE 198
SUB-EXPRESSION (data_i == cmd_info_i[CmdInfoEn4B].opcode)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T5,T6 |
LINE 200
EXPRESSION (((!sck_status_busy_i)) && cmd_info_i[CmdInfoEx4B].valid && (data_i == cmd_info_i[CmdInfoEx4B].opcode))
-----------1---------- --------------2-------------- ---------------------3--------------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T43,T45,T54 |
| 1 | 0 | 1 | Covered | T4,T5,T6 |
| 1 | 1 | 0 | Covered | T8,T13,T53 |
| 1 | 1 | 1 | Covered | T8,T13,T53 |
LINE 200
SUB-EXPRESSION (data_i == cmd_info_i[CmdInfoEx4B].opcode)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T5,T6 |
LINE 202
EXPRESSION (((!sck_status_busy_i)) && cmd_info_i[CmdInfoWrEn].valid && (data_i == cmd_info_i[CmdInfoWrEn].opcode))
-----------1---------- --------------2-------------- ---------------------3--------------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T43,T45,T54 |
| 1 | 0 | 1 | Covered | T4,T5,T6 |
| 1 | 1 | 0 | Covered | T13,T53,T57 |
| 1 | 1 | 1 | Covered | T13,T53,T57 |
LINE 202
SUB-EXPRESSION (data_i == cmd_info_i[CmdInfoWrEn].opcode)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T5,T6 |
LINE 204
EXPRESSION (((!sck_status_busy_i)) && cmd_info_i[CmdInfoWrDi].valid && (data_i == cmd_info_i[CmdInfoWrDi].opcode))
-----------1---------- --------------2-------------- ---------------------3--------------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T43,T45,T54 |
| 1 | 0 | 1 | Covered | T4,T5,T6 |
| 1 | 1 | 0 | Covered | T38,T53,T57 |
| 1 | 1 | 1 | Covered | T38,T53,T57 |
LINE 204
SUB-EXPRESSION (data_i == cmd_info_i[CmdInfoWrDi].opcode)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T5,T6 |
LINE 210
EXPRESSION (cmd_info_i[i].valid && (data_i == cmd_info_i[i].opcode))
---------1--------- ----------------2---------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T6,T7,T8 |
| 1 | 1 | Covered | T6,T7,T8 |
LINE 210
SUB-EXPRESSION (data_i == cmd_info_i[i].opcode)
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T5,T6 |
LINE 240
EXPRESSION ((st == StIdle) && module_active && data_valid_i)
-------1------ ------2------ ------3-----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T6,T7,T8 |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | 1 | Covered | T6,T7,T8 |
LINE 240
SUB-EXPRESSION (st == StIdle)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T6,T7,T8 |
| 1 | Covered | T1,T2,T3 |
LINE 242
EXPRESSION (cmd_info_i[i].valid && (data_i == cmd_info_i[i].opcode))
---------1--------- ----------------2---------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T7,T9,T10 |
| 1 | 0 | Covered | T6,T7,T8 |
| 1 | 1 | Covered | T6,T7,T8 |
LINE 242
SUB-EXPRESSION (data_i == cmd_info_i[i].opcode)
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T6,T7,T8 |
LINE 271
EXPRESSION ((st == StIdle) && module_active && data_valid_i)
-------1------ ------2------ ------3-----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T6,T7,T8 |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | 1 | Covered | T6,T7,T8 |
LINE 271
SUB-EXPRESSION (st == StIdle)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T6,T7,T8 |
| 1 | Covered | T1,T2,T3 |
LINE 279
EXPRESSION (cmd_info_d.upload && ((!sck_status_busy_i)))
--------1-------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T43,T96,T66 |
| 1 | 1 | Covered | T43,T45,T54 |
LINE 295
EXPRESSION ((cmd_info_q.read_pipeline_mode == RdPipeTwoStageHalfCycle) || (cmd_info_q.read_pipeline_mode == RdPipeTwoStageFullCycle))
-----------------------------1---------------------------- -----------------------------2----------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T8,T10,T12 |
| 1 | 0 | Covered | T10,T12,T14 |
LINE 295
SUB-EXPRESSION (cmd_info_q.read_pipeline_mode == RdPipeTwoStageHalfCycle)
-----------------------------1----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T10,T12,T14 |
LINE 295
SUB-EXPRESSION (cmd_info_q.read_pipeline_mode == RdPipeTwoStageFullCycle)
-----------------------------1----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T8,T10,T12 |
LINE 302
EXPRESSION (spi_mode_i == FlashMode)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 303
EXPRESSION (spi_mode_i == PassThrough)
-------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T6,T7,T8 |
LINE 304
EXPRESSION (in_flashmode || in_passthrough)
------1----- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Covered | T6,T7,T8 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 327
EXPRESSION (module_active && data_valid_i && cmd_info_d.valid)
------1------ ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Covered | T6,T7,T8 |
| 1 | 1 | 1 | Covered | T6,T7,T8 |
LINE 384
EXPRESSION (opcode_en4b ? DpEn4B : DpEx4B)
-----1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T53,T43,T45 |
| 1 | Covered | T53,T57,T55 |
LINE 391
EXPRESSION (opcode_wren ? DpWrEn : DpWrDi)
-----1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T53,T57,T43 |
| 1 | Covered | T13,T53,T57 |
LINE 401
EXPRESSION (module_active && data_valid_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T6,T7,T8 |
FSM Coverage for Module :
spi_cmdparse
Summary for FSM :: st
| Total | Covered | Percent | |
| States |
9 |
9 |
100.00 |
(Not included in score) |
| Transitions |
8 |
8 |
100.00 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: st
| states | Line No. | Covered | Tests |
| StAddr4B |
381 |
Covered |
T53,T57,T55 |
| StIdle |
240 |
Covered |
T1,T2,T3 |
| StJedec |
346 |
Covered |
T53,T43,T45 |
| StReadCmd |
372 |
Covered |
T6,T7,T8 |
| StSfdp |
358 |
Covered |
T53,T43,T45 |
| StStatus |
335 |
Covered |
T9,T53,T55 |
| StUpload |
376 |
Covered |
T43,T45,T54 |
| StWait |
340 |
Covered |
T6,T7,T8 |
| StWrEn |
388 |
Covered |
T13,T53,T57 |
| transitions | Line No. | Covered | Tests |
| StIdle->StAddr4B |
381 |
Covered |
T53,T57,T55 |
| StIdle->StJedec |
346 |
Covered |
T53,T43,T45 |
| StIdle->StReadCmd |
372 |
Covered |
T6,T7,T8 |
| StIdle->StSfdp |
358 |
Covered |
T53,T43,T45 |
| StIdle->StStatus |
335 |
Covered |
T9,T53,T55 |
| StIdle->StUpload |
376 |
Covered |
T43,T45,T54 |
| StIdle->StWait |
340 |
Covered |
T6,T7,T8 |
| StIdle->StWrEn |
388 |
Covered |
T13,T53,T57 |
Branch Coverage for Module :
spi_cmdparse
| Line No. | Total | Covered | Percent |
| Branches |
|
49 |
47 |
95.92 |
| IF |
187 |
2 |
2 |
100.00 |
| IF |
210 |
2 |
2 |
100.00 |
| IF |
218 |
3 |
3 |
100.00 |
| IF |
240 |
2 |
2 |
100.00 |
| IF |
271 |
2 |
2 |
100.00 |
| IF |
283 |
8 |
8 |
100.00 |
| IF |
307 |
3 |
2 |
66.67 |
| CASE |
325 |
27 |
26 |
96.30 |
187 if (cmd_info_i[CmdInfoReadStatus1+i].valid
-1-
188 && (data_i == cmd_info_i[CmdInfoReadStatus1+i].opcode)) begin
189 opcode_readstatus = 1'b 1;
==>
190 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T6,T7,T8 |
| 0 |
Covered |
T1,T2,T3 |
210 if (cmd_info_i[i].valid && data_i == cmd_info_i[i].opcode) begin
-1-
211 opcode_readcmd = 1'b 1;
==>
212 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T6,T7,T8 |
| 0 |
Covered |
T1,T2,T3 |
218 if (!rst_ni) begin
-1-
219 cmd_info_q <= '{
==>
220 payload_dir: payload_dir_e'(PayloadIn),
221 addr_mode: addr_mode_e'(0),
222 read_pipeline_mode: read_pipeline_mode_e'(0),
223 default: '0
224 };
225 cmd_info_idx_q <= '0;
226 end else if (latch_cmdinfo) begin
-2-
227 cmd_info_q <= cmd_info_d;
==>
228 cmd_info_idx_q <= cmd_info_idx_d;
229 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T6,T7,T8 |
| 0 |
0 |
Covered |
T6,T7,T8 |
240 if ((st == StIdle) && module_active && data_valid_i) begin
-1-
241 for (int unsigned i = 0 ; i < NumTotalCmdInfo ; i++ ) begin
==>
242 if (cmd_info_i[i].valid && (data_i == cmd_info_i[i].opcode)) begin
243 cmd_info_d = cmd_info_i[i];
244 cmd_info_idx_d = CmdInfoIdxW'(i);
245 end
246 end
247 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
271 if ((st == StIdle) && module_active && data_valid_i) begin
-1-
272 cmd_only_info_o = cmd_info_d;
==>
273 cmd_only_info_idx_o = cmd_info_idx_d;
274 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
283 if (!rst_ni) begin
-1-
284 intercept_status_o <= 1'b 0;
==>
285 intercept_jedec_o <= 1'b 0;
286 intercept_sfdp_o <= 1'b 0;
287 end else if (intercept_d) begin
-2-
288 if (opcode_readstatus) intercept_status_o <= 1'b 1;
-3-
==>
MISSING_ELSE
==>
289 if (opcode_readjedec) intercept_jedec_o <= 1'b 1;
-4-
==>
MISSING_ELSE
==>
290 if (opcode_readsfdp) intercept_sfdp_o <= 1'b 1;
-5-
==>
MISSING_ELSE
==>
291 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | Status | Tests |
| 1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
1 |
- |
- |
Covered |
T9,T55,T60 |
| 0 |
1 |
0 |
- |
- |
Covered |
T45,T51,T52 |
| 0 |
1 |
- |
1 |
- |
Covered |
T45,T51,T66 |
| 0 |
1 |
- |
0 |
- |
Covered |
T9,T55,T60 |
| 0 |
1 |
- |
- |
1 |
Covered |
T45,T51,T52 |
| 0 |
1 |
- |
- |
0 |
Covered |
T9,T55,T60 |
| 0 |
0 |
- |
- |
- |
Covered |
T6,T7,T8 |
307 if (!rst_ni) begin
-1-
308 st <= StIdle;
==>
309 end else if (module_active) begin
-2-
310 st <= st_d;
==>
311 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T6,T7,T8 |
| 0 |
0 |
Not Covered |
|
325 unique case (st)
-1-
326 StIdle: begin
327 if (module_active && data_valid_i && cmd_info_d.valid) begin
-2-
328 // 8th bit is valid here
329 latch_cmdinfo = 1'b 1;
330 cmd_sync_pulse_o = 1'b1;
331
332 priority case (1'b 1)
-3-
333 opcode_readstatus: begin
334 if (in_flashmode) begin
-4-
335 st_d = StStatus;
==>
336 end else if (cfg_intercept_en_status_i) begin
-5-
337 st_d = StStatus;
==>
338 intercept_d = 1'b 1;
339 end else begin
340 st_d = StWait;
==>
341 end
342 end
343
344 opcode_readjedec: begin
345 if (in_flashmode) begin
-6-
346 st_d = StJedec;
==>
347 end else if (cfg_intercept_en_jedec_i) begin
-7-
348 st_d = StJedec;
==>
349 intercept_d = 1'b 1;
350 end else begin
351 st_d = StWait;
==>
352 end
353 end
354
355 // Read SFDP may combine with Read command later
356 opcode_readsfdp: begin
357 if (in_flashmode) begin
-8-
358 st_d = StSfdp;
==>
359 end else if (cfg_intercept_en_sfdp_i) begin
-9-
360 st_d = StSfdp;
==>
361 intercept_d = 1'b 1;
362 end else begin
363 // Check passthrough
364 st_d = StWait;
==>
365 end
366 end
367
368 opcode_readcmd: begin
369 // Let it move to ReadCmd regardless of the modes
370 // Then, ReadCmd will handle Mailbox command if received address
371 // falls into Mailbox address range
372 st_d = StReadCmd;
==>
373 end
374
375 upload: begin
376 st_d = StUpload;
==>
377 cmd_only_sel_dp = DpUpload;
378 end
379
380 opcode_en4b, opcode_ex4b: begin
381 st_d = StAddr4B;
382
383 // opcode only commands. Need to assert DP before transition
384 cmd_only_sel_dp = (opcode_en4b) ? DpEn4B : DpEx4B ;
-10-
==>
==>
385 end
386
387 opcode_wren, opcode_wrdi: begin
388 st_d = StWrEn;
389
390 // opcode only commands. Need to assert DP before transition
391 cmd_only_sel_dp = (opcode_wren) ? DpWrEn : DpWrDi ;
-11-
==>
==>
392 end
393
394 default: begin
395 st_d = StWait;
==>
396
397 // DpNone
398 end
399 endcase
400 end // if (module_active && data_valid_i && cmd_info_d.valid)
401 else if (module_active && data_valid_i) begin
-12-
402 // Could not find valid command information entry.
403 st_d = StWait;
==>
404 cmd_sync_pulse_o = 1'b1;
405 end // if (module_active && data_valid_i)
MISSING_ELSE
==>
406 end
407
408 // dead-end states below. Reset (CSb de-assertion) let SM back to Idle
409 StStatus: sel_dp = DpReadStatus;
==>
410
411 StJedec: sel_dp = DpReadJEDEC;
==>
412
413 StSfdp: sel_dp = DpReadSFDP;
==>
414
415 StReadCmd: sel_dp = DpReadCmd;
==>
416
417 StUpload: sel_dp = DpUpload;
==>
418
419 StAddr4B: sel_dp = DpNone; // Terminal state wait reset
==>
420
421 StWrEn: sel_dp = DpNone; // Terminal state wait reset
==>
422
423 StWait: begin
424 st_d = StWait;
==>
425
426 sel_dp = DpNone;
427 end
428
429 default: begin
430 sel_dp = DpNone;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | Status | Tests |
| StIdle |
1 |
opcode_readstatus |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T53,T43,T54 |
| StIdle |
1 |
opcode_readstatus |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T9,T55,T60 |
| StIdle |
1 |
opcode_readstatus |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T6,T17,T18 |
| StIdle |
1 |
opcode_readjedec |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T53,T43,T54 |
| StIdle |
1 |
opcode_readjedec |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
Covered |
T45,T51,T66 |
| StIdle |
1 |
opcode_readjedec |
- |
- |
0 |
0 |
- |
- |
- |
- |
- |
Covered |
T6,T10,T39 |
| StIdle |
1 |
opcode_readsfdp |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
Covered |
T53,T43,T54 |
| StIdle |
1 |
opcode_readsfdp |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
Covered |
T45,T51,T52 |
| StIdle |
1 |
opcode_readsfdp |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
Covered |
T10,T56,T50 |
| StIdle |
1 |
opcode_readcmd |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T6,T7,T8 |
| StIdle |
1 |
upload |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T43,T45,T54 |
| StIdle |
1 |
opcode_en4b opcode_ex4b |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T53,T57,T55 |
| StIdle |
1 |
opcode_en4b opcode_ex4b |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
Covered |
T53,T43,T45 |
| StIdle |
1 |
opcode_wren opcode_wrdi |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
Covered |
T13,T53,T57 |
| StIdle |
1 |
opcode_wren opcode_wrdi |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
Covered |
T53,T57,T43 |
| StIdle |
1 |
default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T6,T10,T18 |
| StIdle |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T1,T2,T3 |
| StIdle |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T1,T2,T3 |
| StStatus |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T9,T53,T55 |
| StJedec |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T53,T43,T45 |
| StSfdp |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T53,T43,T45 |
| StReadCmd |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T6,T7,T8 |
| StUpload |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T43,T45,T54 |
| StAddr4B |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T53,T57,T55 |
| StWrEn |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T13,T53,T57 |
| StWait |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T6,T7,T8 |
| default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
Assert Coverage for Module :
spi_cmdparse
Assertion Details
CmdOnlySelDpKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
153693968 |
127219412 |
0 |
0 |
| T6 |
48835 |
48592 |
0 |
0 |
| T7 |
4226 |
4226 |
0 |
0 |
| T8 |
6798 |
6798 |
0 |
0 |
| T9 |
23898 |
23376 |
0 |
0 |
| T10 |
123826 |
123826 |
0 |
0 |
| T11 |
72104 |
0 |
0 |
0 |
| T12 |
13543 |
13543 |
0 |
0 |
| T13 |
18624 |
18624 |
0 |
0 |
| T14 |
7084 |
7084 |
0 |
0 |
| T17 |
0 |
12416 |
0 |
0 |
| T18 |
0 |
42920 |
0 |
0 |
| T25 |
216 |
0 |
0 |
0 |
OnlyOneDatapath_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
153693968 |
64007 |
0 |
0 |
| T6 |
48835 |
22 |
0 |
0 |
| T7 |
4226 |
4 |
0 |
0 |
| T8 |
6798 |
4 |
0 |
0 |
| T9 |
23898 |
10 |
0 |
0 |
| T10 |
123826 |
22 |
0 |
0 |
| T11 |
72104 |
0 |
0 |
0 |
| T12 |
13543 |
8 |
0 |
0 |
| T13 |
18624 |
20 |
0 |
0 |
| T14 |
7084 |
8 |
0 |
0 |
| T17 |
0 |
8 |
0 |
0 |
| T18 |
0 |
22 |
0 |
0 |
| T25 |
216 |
0 |
0 |
0 |
SelDpKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
153693968 |
127219412 |
0 |
0 |
| T6 |
48835 |
48592 |
0 |
0 |
| T7 |
4226 |
4226 |
0 |
0 |
| T8 |
6798 |
6798 |
0 |
0 |
| T9 |
23898 |
23376 |
0 |
0 |
| T10 |
123826 |
123826 |
0 |
0 |
| T11 |
72104 |
0 |
0 |
0 |
| T12 |
13543 |
13543 |
0 |
0 |
| T13 |
18624 |
18624 |
0 |
0 |
| T14 |
7084 |
7084 |
0 |
0 |
| T17 |
0 |
12416 |
0 |
0 |
| T18 |
0 |
42920 |
0 |
0 |
| T25 |
216 |
0 |
0 |
0 |
StKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
153693968 |
127219412 |
0 |
0 |
| T6 |
48835 |
48592 |
0 |
0 |
| T7 |
4226 |
4226 |
0 |
0 |
| T8 |
6798 |
6798 |
0 |
0 |
| T9 |
23898 |
23376 |
0 |
0 |
| T10 |
123826 |
123826 |
0 |
0 |
| T11 |
72104 |
0 |
0 |
0 |
| T12 |
13543 |
13543 |
0 |
0 |
| T13 |
18624 |
18624 |
0 |
0 |
| T14 |
7084 |
7084 |
0 |
0 |
| T17 |
0 |
12416 |
0 |
0 |
| T18 |
0 |
42920 |
0 |
0 |
| T25 |
216 |
0 |
0 |
0 |