Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2789752	1			T1	1		T2	1		T3	14
all_values[1]	2789752	1			T1	1		T2	1		T3	14
all_values[2]	2789752	1			T1	1		T2	1		T3	14
all_values[3]	2789752	1			T1	1		T2	1		T3	14
all_values[4]	2789752	1			T1	1		T2	1		T3	14
all_values[5]	2789752	1			T1	1		T2	1		T3	14
all_values[6]	2789752	1			T1	1		T2	1		T3	14
all_values[7]	2789752	1			T1	1		T2	1		T3	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22000498

1

T1

8

T2

8

T3

112

auto[1]

317518

1

T15

143

T84

117

T33

98

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22292967

1

T1

8

T2

8

T3

112

auto[1]

25049

1

T47

1

T15

118

T133

1

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2719182	1			T1	1		T2	1		T3	14
all_values[0]	auto[0]	auto[1]	11693	1			T15	5		T43	18		T55	72
all_values[0]	auto[1]	auto[0]	58447	1			T15	10		T84	4		T33	6
all_values[0]	auto[1]	auto[1]	430	1			T15	7		T84	7		T33	6
all_values[1]	auto[0]	auto[0]	2768180	1			T1	1		T2	1		T3	14
all_values[1]	auto[0]	auto[1]	7898	1			T15	3		T43	13		T55	58
all_values[1]	auto[1]	auto[0]	13363	1			T15	10		T84	6		T33	6
all_values[1]	auto[1]	auto[1]	311	1			T15	15		T84	7		T33	2
all_values[2]	auto[0]	auto[0]	2763120	1			T1	1		T2	1		T3	14
all_values[2]	auto[0]	auto[1]	2608	1			T15	5		T55	22		T84	9
all_values[2]	auto[1]	auto[0]	23833	1			T15	11		T84	8		T33	5
all_values[2]	auto[1]	auto[1]	191	1			T15	6		T84	6		T33	4
all_values[3]	auto[0]	auto[0]	2755892	1			T1	1		T2	1		T3	14
all_values[3]	auto[0]	auto[1]	216	1			T15	13		T84	5		T33	5
all_values[3]	auto[1]	auto[0]	33456	1			T15	11		T84	13		T33	5
all_values[3]	auto[1]	auto[1]	188	1			T15	7		T84	5		T33	6
all_values[4]	auto[0]	auto[0]	2722568	1			T1	1		T2	1		T3	14
all_values[4]	auto[0]	auto[1]	196	1			T47	1		T15	6		T133	1
all_values[4]	auto[1]	auto[0]	66798	1			T15	9		T84	7		T33	8
all_values[4]	auto[1]	auto[1]	190	1			T15	4		T84	8		T33	5
all_values[5]	auto[0]	auto[0]	2750267	1			T1	1		T2	1		T3	14
all_values[5]	auto[0]	auto[1]	172	1			T15	9		T84	4		T33	3
all_values[5]	auto[1]	auto[0]	39124	1			T15	11		T84	12		T33	11
all_values[5]	auto[1]	auto[1]	189	1			T15	5		T84	3		T33	7
all_values[6]	auto[0]	auto[0]	2742607	1			T1	1		T2	1		T3	14
all_values[6]	auto[0]	auto[1]	194	1			T15	6		T84	7		T33	3
all_values[6]	auto[1]	auto[0]	46755	1			T15	10		T84	7		T33	7
all_values[6]	auto[1]	auto[1]	196	1			T15	7		T84	8		T33	6
all_values[7]	auto[0]	auto[0]	2755518	1			T1	1		T2	1		T3	14
all_values[7]	auto[0]	auto[1]	187	1			T15	7		T84	6		T33	5
all_values[7]	auto[1]	auto[0]	33857	1			T15	7		T84	11		T33	3
all_values[7]	auto[1]	auto[1]	190	1			T15	13		T84	5		T33	11