Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.36 98.36 93.99 93.90 89.36 97.19 95.45 99.26


Total tests in report: 1122
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
65.01 65.01 91.96 91.96 79.77 79.77 81.20 81.20 28.89 28.89 88.77 88.77 71.69 71.69 12.77 12.77 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.4059099079
72.49 7.48 93.25 1.29 82.70 2.93 81.30 0.10 55.56 26.67 90.53 1.76 76.39 4.69 27.72 14.95 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.3864060962
79.78 7.29 96.22 2.96 88.38 5.68 84.25 2.95 77.78 22.22 94.61 4.08 84.35 7.97 32.87 5.15 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_all.3761977456
82.36 2.58 96.60 0.38 88.97 0.58 84.25 0.00 86.67 8.89 95.06 0.46 84.35 0.00 40.64 7.77 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.4116763293
84.55 2.18 97.02 0.42 90.03 1.06 85.63 1.38 86.67 0.00 95.55 0.49 84.35 0.00 52.57 11.93 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_stress_all.2106079936
86.22 1.67 97.04 0.03 90.10 0.07 85.63 0.00 88.89 2.22 95.59 0.03 84.50 0.14 61.78 9.21 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_all.2152509247
87.85 1.64 97.04 0.00 90.27 0.17 86.42 0.79 88.89 0.00 95.62 0.03 93.17 8.68 63.56 1.78 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1651078934
89.32 1.46 97.56 0.51 91.13 0.86 89.17 2.76 93.33 4.44 96.30 0.68 93.17 0.00 64.55 0.99 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_upload.3844568603
90.26 0.95 97.56 0.00 91.13 0.00 89.17 0.00 93.33 0.00 96.30 0.00 93.17 0.00 71.19 6.63 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.1778188655
90.89 0.63 98.23 0.67 91.73 0.60 90.45 1.28 93.33 0.00 96.97 0.68 93.60 0.43 71.93 0.74 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode.3858783047
91.50 0.61 98.23 0.00 91.74 0.01 91.04 0.59 93.33 0.00 96.97 0.00 93.60 0.00 75.59 3.66 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_stress_all.4046631267
92.01 0.50 98.23 0.01 91.74 0.00 91.04 0.00 93.33 0.00 96.99 0.02 93.74 0.14 78.96 3.37 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.1613463114
92.45 0.44 98.24 0.01 91.78 0.04 93.50 2.46 93.33 0.00 97.01 0.02 94.03 0.28 79.26 0.30 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_sec_cm.4196135825
92.82 0.37 98.24 0.00 91.78 0.00 93.50 0.00 93.33 0.00 97.01 0.00 94.03 0.00 81.83 2.57 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.1127028427
93.11 0.30 98.24 0.00 91.78 0.00 93.50 0.00 93.33 0.00 97.01 0.00 94.03 0.00 83.91 2.08 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.3048682986
93.41 0.29 98.26 0.02 91.85 0.07 93.50 0.00 93.33 0.00 97.04 0.03 94.03 0.00 85.84 1.93 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_all.865552210
93.63 0.22 98.26 0.00 91.87 0.01 93.50 0.00 93.33 0.00 97.04 0.00 94.03 0.00 87.38 1.53 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.4019912307
93.80 0.17 98.28 0.02 92.54 0.67 93.50 0.00 93.33 0.00 97.07 0.03 94.31 0.28 87.52 0.15 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode.655900394
93.95 0.16 98.28 0.00 92.55 0.01 93.50 0.00 93.33 0.00 97.07 0.00 94.31 0.00 88.61 1.09 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_stress_all.1161110993
94.10 0.15 98.29 0.01 92.63 0.07 93.50 0.00 93.33 0.00 97.09 0.02 94.31 0.00 89.55 0.94 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.2304516320
94.25 0.15 98.29 0.00 92.63 0.00 93.50 0.00 93.33 0.00 97.09 0.00 94.31 0.00 90.59 1.04 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_all.65784237
94.37 0.12 98.29 0.00 92.63 0.00 93.50 0.00 93.33 0.00 97.09 0.00 95.16 0.85 90.59 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.3519520875
94.49 0.12 98.29 0.00 92.63 0.00 93.50 0.00 93.33 0.00 97.09 0.00 95.16 0.00 91.44 0.84 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_stress_all.2705537181
94.60 0.11 98.29 0.00 93.28 0.66 93.50 0.00 93.33 0.00 97.09 0.00 95.16 0.00 91.53 0.10 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.1608805687
94.71 0.11 98.29 0.00 93.38 0.10 93.50 0.00 93.33 0.00 97.09 0.00 95.16 0.00 92.18 0.64 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.1377095190
94.81 0.11 98.29 0.00 93.38 0.00 93.50 0.00 93.33 0.00 97.09 0.00 95.16 0.00 92.92 0.74 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_mode_ignore_cmds.800430575
94.92 0.10 98.32 0.03 93.42 0.04 93.50 0.00 93.33 0.00 97.16 0.07 95.16 0.00 93.51 0.59 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_stress_all.974982221
95.01 0.09 98.32 0.00 93.42 0.00 93.50 0.00 93.33 0.00 97.16 0.00 95.16 0.00 94.16 0.64 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_stress_all.468016449
95.09 0.08 98.32 0.00 93.57 0.15 93.50 0.00 93.33 0.00 97.16 0.00 95.16 0.00 94.60 0.45 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_mailbox.3991262830
95.18 0.08 98.32 0.00 93.57 0.00 93.50 0.00 93.33 0.00 97.16 0.00 95.16 0.00 95.20 0.59 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm.4185804678
95.24 0.06 98.32 0.00 93.57 0.00 93.50 0.00 93.33 0.00 97.16 0.00 95.16 0.00 95.64 0.45 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_mode_ignore_cmds.2637835034
95.30 0.06 98.32 0.00 93.57 0.00 93.50 0.00 93.33 0.00 97.16 0.00 95.45 0.28 95.79 0.15 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_stress_all.2375145140
95.35 0.05 98.32 0.00 93.57 0.00 93.50 0.00 93.33 0.00 97.16 0.00 95.45 0.00 96.14 0.35 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_stress_all.254191540
95.40 0.05 98.32 0.00 93.57 0.00 93.50 0.00 93.33 0.00 97.16 0.00 95.45 0.00 96.49 0.35 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_stress_all.1507745164
95.45 0.05 98.32 0.00 93.57 0.00 93.70 0.20 93.33 0.00 97.16 0.00 95.45 0.00 96.63 0.15 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_intercept.631287636
95.49 0.04 98.32 0.00 93.57 0.00 93.70 0.00 93.33 0.00 97.16 0.00 95.45 0.00 96.93 0.30 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_and_tpm.2310952575
95.53 0.04 98.35 0.03 93.61 0.04 93.90 0.20 93.33 0.00 97.16 0.00 95.45 0.00 96.93 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_alert_test.1793906494
95.57 0.04 98.35 0.00 93.66 0.05 93.90 0.00 93.33 0.00 97.16 0.00 95.45 0.00 97.13 0.20 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode.1861869238
95.60 0.04 98.35 0.00 93.66 0.00 93.90 0.00 93.33 0.00 97.16 0.00 95.45 0.00 97.38 0.25 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_mode_ignore_cmds.462143290
95.63 0.03 98.35 0.00 93.67 0.01 93.90 0.00 93.33 0.00 97.16 0.00 95.45 0.00 97.57 0.20 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.3720635501
95.66 0.03 98.35 0.00 93.82 0.15 93.90 0.00 93.33 0.00 97.16 0.00 95.45 0.00 97.62 0.05 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.1006453867
95.69 0.03 98.35 0.00 93.82 0.00 93.90 0.00 93.33 0.00 97.16 0.00 95.45 0.00 97.82 0.20 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.3266121571
95.72 0.03 98.35 0.00 93.82 0.00 93.90 0.00 93.33 0.00 97.16 0.00 95.45 0.00 98.02 0.20 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_all.1832741065
95.74 0.03 98.35 0.00 93.87 0.05 93.90 0.00 93.33 0.00 97.19 0.03 95.45 0.00 98.12 0.10 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_cfg_cmd.544441975
95.76 0.02 98.35 0.00 93.87 0.00 93.90 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.27 0.15 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_upload.716999038
95.79 0.02 98.35 0.00 93.87 0.00 93.90 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.42 0.15 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_intercept.2670637672
95.80 0.01 98.35 0.00 93.87 0.00 93.90 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.51 0.10 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.2141174334
95.81 0.01 98.35 0.00 93.87 0.00 93.90 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.61 0.10 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm_min_idle.759144033
95.83 0.01 98.35 0.00 93.87 0.00 93.90 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.71 0.10 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.2623801810
95.84 0.01 98.35 0.00 93.88 0.01 93.90 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.76 0.05 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.3290730700
95.85 0.01 98.35 0.00 93.89 0.01 93.90 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.81 0.05 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_and_tpm.1856406994
95.85 0.01 98.36 0.02 93.93 0.04 93.90 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.81 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_csb_read.3876066725
95.86 0.01 98.36 0.00 93.93 0.00 93.90 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.86 0.05 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.1327064552
95.87 0.01 98.36 0.00 93.93 0.00 93.90 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.91 0.05 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_and_tpm_min_idle.971922333
95.88 0.01 98.36 0.00 93.93 0.00 93.90 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.96 0.05 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_and_tpm.1191391248
95.88 0.01 98.36 0.00 93.93 0.00 93.90 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.01 0.05 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_mode_ignore_cmds.605673092
95.89 0.01 98.36 0.00 93.93 0.00 93.90 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.06 0.05 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode.4091731638
95.90 0.01 98.36 0.00 93.93 0.00 93.90 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.11 0.05 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_mode.745346208
95.90 0.01 98.36 0.00 93.93 0.00 93.90 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.16 0.05 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_mode.3911314207
95.91 0.01 98.36 0.00 93.93 0.00 93.90 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.21 0.05 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_and_tpm_min_idle.236309653
95.92 0.01 98.36 0.00 93.93 0.00 93.90 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.26 0.05 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_mode_ignore_cmds.3971669236
95.92 0.01 98.36 0.00 93.96 0.02 93.90 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2514785722
95.92 0.01 98.36 0.00 93.98 0.02 93.90 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_cfg_cmd.504089220
95.93 0.01 98.36 0.00 93.99 0.01 93.90 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.185168736

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.4127736412
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3934154220
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1430992637
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.2428826839
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.2503004719
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.1873175476
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.3739683982
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.292897907
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.3972424436
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.3156500845
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3863669760
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1451159847
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.1123695883
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.889748704
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.1937758868
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3837358267
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/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_cfg_cmd.767572253
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/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_intercept.2275706898
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/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_all.4129763793
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.4201183533
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_rw.2285723304
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.1702612812
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_upload.2713512305



Total test records in report: 1122
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_intercept.4098513500 Sep 09 11:28:46 AM UTC 24 Sep 09 11:28:52 AM UTC 24 181283884 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_csb_read.3876066725 Sep 09 11:28:43 AM UTC 24 Sep 09 11:28:55 AM UTC 24 15999388 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_upload.695304127 Sep 09 11:28:49 AM UTC 24 Sep 09 11:28:56 AM UTC 24 471334372 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.1898926038 Sep 09 11:28:50 AM UTC 24 Sep 09 11:28:57 AM UTC 24 474719078 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_cfg_cmd.3522254481 Sep 09 11:29:32 AM UTC 24 Sep 09 11:29:36 AM UTC 24 194629244 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_all.350165742 Sep 09 11:29:24 AM UTC 24 Sep 09 11:29:37 AM UTC 24 912965140 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_all.2143825570 Sep 09 11:28:50 AM UTC 24 Sep 09 11:28:59 AM UTC 24 148764096 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode.3858783047 Sep 09 11:28:50 AM UTC 24 Sep 09 11:28:59 AM UTC 24 861367371 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_cfg_cmd.716088771 Sep 09 11:28:56 AM UTC 24 Sep 09 11:29:02 AM UTC 24 1378028660 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.4059099079 Sep 09 11:28:56 AM UTC 24 Sep 09 11:29:02 AM UTC 24 3083013662 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_intercept.631287636 Sep 09 11:28:56 AM UTC 24 Sep 09 11:29:03 AM UTC 24 1494243439 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_upload.3844568603 Sep 09 11:29:26 AM UTC 24 Sep 09 11:29:38 AM UTC 24 3032040700 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.3299434303 Sep 09 11:28:55 AM UTC 24 Sep 09 11:29:04 AM UTC 24 173698752 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_rw.543485686 Sep 09 11:28:55 AM UTC 24 Sep 09 11:29:04 AM UTC 24 23864767 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.1013429223 Sep 09 11:28:50 AM UTC 24 Sep 09 11:29:05 AM UTC 24 855617882 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_all.3761977456 Sep 09 11:28:55 AM UTC 24 Sep 09 11:29:07 AM UTC 24 1050576421 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.1377095190 Sep 09 11:28:55 AM UTC 24 Sep 09 11:29:09 AM UTC 24 1089810312 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.797661143 Sep 09 11:29:00 AM UTC 24 Sep 09 11:29:09 AM UTC 24 29824755 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_mailbox.1061500840 Sep 09 11:28:56 AM UTC 24 Sep 09 11:29:09 AM UTC 24 1822746214 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_intercept.447907188 Sep 09 11:29:04 AM UTC 24 Sep 09 11:29:11 AM UTC 24 127492279 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.1095462893 Sep 09 11:29:07 AM UTC 24 Sep 09 11:29:12 AM UTC 24 118988784 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_rw.583447510 Sep 09 11:29:00 AM UTC 24 Sep 09 11:29:12 AM UTC 24 5646202632 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.4158887082 Sep 09 11:28:56 AM UTC 24 Sep 09 11:29:12 AM UTC 24 27271539024 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode.4091731638 Sep 09 11:29:06 AM UTC 24 Sep 09 11:29:13 AM UTC 24 180821419 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.2658695453 Sep 09 11:28:59 AM UTC 24 Sep 09 11:29:15 AM UTC 24 461555286 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_cfg_cmd.504089220 Sep 09 11:28:50 AM UTC 24 Sep 09 11:29:15 AM UTC 24 11436783680 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_upload.3369648568 Sep 09 11:29:05 AM UTC 24 Sep 09 11:29:15 AM UTC 24 147818723 ps
T79 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_alert_test.3814033341 Sep 09 11:28:58 AM UTC 24 Sep 09 11:29:19 AM UTC 24 14515476 ps
T77 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_csb_read.3079035777 Sep 09 11:28:58 AM UTC 24 Sep 09 11:29:20 AM UTC 24 18354061 ps
T87 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_mailbox.2186236320 Sep 09 11:29:04 AM UTC 24 Sep 09 11:29:20 AM UTC 24 7031909341 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_sec_cm.4196135825 Sep 09 11:28:58 AM UTC 24 Sep 09 11:29:20 AM UTC 24 150151967 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_stress_all.2189199317 Sep 09 11:28:55 AM UTC 24 Sep 09 11:29:20 AM UTC 24 52042350 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_sec_cm.1948322233 Sep 09 11:29:11 AM UTC 24 Sep 09 11:29:20 AM UTC 24 129564433 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_intercept.2192181286 Sep 09 11:29:16 AM UTC 24 Sep 09 11:29:20 AM UTC 24 348253685 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_rw.150821038 Sep 09 11:29:14 AM UTC 24 Sep 09 11:29:20 AM UTC 24 138291929 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_upload.836286860 Sep 09 11:28:56 AM UTC 24 Sep 09 11:29:23 AM UTC 24 10702966702 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_csb_read.832169300 Sep 09 11:29:22 AM UTC 24 Sep 09 11:29:24 AM UTC 24 108851817 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_sec_cm.2902977439 Sep 09 11:29:22 AM UTC 24 Sep 09 11:29:24 AM UTC 24 35706324 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_cfg_cmd.602905031 Sep 09 11:29:05 AM UTC 24 Sep 09 11:29:24 AM UTC 24 1280849512 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_alert_test.3869299985 Sep 09 11:29:22 AM UTC 24 Sep 09 11:29:25 AM UTC 24 12863999 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.2497387945 Sep 09 11:29:24 AM UTC 24 Sep 09 11:29:36 AM UTC 24 2920018694 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_rw.1320756691 Sep 09 11:29:31 AM UTC 24 Sep 09 11:29:36 AM UTC 24 234038632 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_intercept.512345150 Sep 09 11:29:31 AM UTC 24 Sep 09 11:29:37 AM UTC 24 578741409 ps
T103 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.3540334467 Sep 09 11:29:13 AM UTC 24 Sep 09 11:29:25 AM UTC 24 16031328 ps
T220 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.2485689063 Sep 09 11:29:15 AM UTC 24 Sep 09 11:29:25 AM UTC 24 163346588 ps
T115 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.430756344 Sep 09 11:29:13 AM UTC 24 Sep 09 11:29:26 AM UTC 24 199262935 ps
T116 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.467417331 Sep 09 11:29:24 AM UTC 24 Sep 09 11:29:26 AM UTC 24 128292716 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_stress_all.3514732172 Sep 09 11:29:21 AM UTC 24 Sep 09 11:29:26 AM UTC 24 146511274 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.1714063835 Sep 09 11:29:07 AM UTC 24 Sep 09 11:29:26 AM UTC 24 16168398435 ps
T133 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode.655900394 Sep 09 11:29:20 AM UTC 24 Sep 09 11:29:27 AM UTC 24 231493050 ps
T118 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_cfg_cmd.4050880870 Sep 09 11:29:19 AM UTC 24 Sep 09 11:29:28 AM UTC 24 2205119561 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_stress_all.2595765334 Sep 09 11:29:30 AM UTC 24 Sep 09 11:29:45 AM UTC 24 172557701 ps
T105 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.3096522243 Sep 09 11:29:21 AM UTC 24 Sep 09 11:29:29 AM UTC 24 451018714 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_all.5756320 Sep 09 11:29:13 AM UTC 24 Sep 09 11:29:29 AM UTC 24 1942444443 ps
T179 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.68586 Sep 09 11:28:56 AM UTC 24 Sep 09 11:29:29 AM UTC 24 5210373580 ps
T418 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_csb_read.2333049773 Sep 09 11:28:55 AM UTC 24 Sep 09 11:29:30 AM UTC 24 30954567 ps
T80 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_alert_test.2774141279 Sep 09 11:29:11 AM UTC 24 Sep 09 11:29:30 AM UTC 24 36872109 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_sec_cm.2726717522 Sep 09 11:28:55 AM UTC 24 Sep 09 11:29:30 AM UTC 24 35406996 ps
T419 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_alert_test.1793906494 Sep 09 11:28:55 AM UTC 24 Sep 09 11:29:30 AM UTC 24 19674269 ps
T420 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_csb_read.3104588136 Sep 09 11:29:11 AM UTC 24 Sep 09 11:29:30 AM UTC 24 120209305 ps
T132 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_mailbox.3991262830 Sep 09 11:29:16 AM UTC 24 Sep 09 11:29:32 AM UTC 24 2544379064 ps
T180 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode.354302098 Sep 09 11:29:26 AM UTC 24 Sep 09 11:29:32 AM UTC 24 127634132 ps
T207 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.881174882 Sep 09 11:29:03 AM UTC 24 Sep 09 11:29:32 AM UTC 24 2486306672 ps
T181 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.3152988255 Sep 09 11:29:27 AM UTC 24 Sep 09 11:29:33 AM UTC 24 293310380 ps
T304 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_cfg_cmd.4132559923 Sep 09 11:29:26 AM UTC 24 Sep 09 11:29:34 AM UTC 24 1165286122 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.2035159816 Sep 09 11:29:03 AM UTC 24 Sep 09 11:29:34 AM UTC 24 858772455 ps
T421 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_mailbox.2099173669 Sep 09 11:29:31 AM UTC 24 Sep 09 11:29:35 AM UTC 24 102337121 ps
T422 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode.1052322468 Sep 09 11:28:56 AM UTC 24 Sep 09 11:29:36 AM UTC 24 1814816835 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.1668911149 Sep 09 11:29:31 AM UTC 24 Sep 09 11:29:38 AM UTC 24 1732149671 ps
T423 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_alert_test.2367807556 Sep 09 11:29:30 AM UTC 24 Sep 09 11:29:45 AM UTC 24 77589891 ps
T424 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_csb_read.3453420768 Sep 09 11:29:30 AM UTC 24 Sep 09 11:29:39 AM UTC 24 16102057 ps
T117 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.2574359176 Sep 09 11:29:30 AM UTC 24 Sep 09 11:29:39 AM UTC 24 52541255 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_sec_cm.566297497 Sep 09 11:29:30 AM UTC 24 Sep 09 11:29:45 AM UTC 24 110350723 ps
T425 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_csb_read.3384530361 Sep 09 11:29:37 AM UTC 24 Sep 09 11:29:39 AM UTC 24 42691699 ps
T426 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_alert_test.4023539485 Sep 09 11:29:37 AM UTC 24 Sep 09 11:29:40 AM UTC 24 33306311 ps
T241 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_upload.4084830072 Sep 09 11:29:31 AM UTC 24 Sep 09 11:29:40 AM UTC 24 1302791246 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_rw.1580072066 Sep 09 11:29:25 AM UTC 24 Sep 09 11:29:41 AM UTC 24 436832396 ps
T427 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.3431486483 Sep 09 11:29:30 AM UTC 24 Sep 09 11:29:42 AM UTC 24 470290074 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.527510028 Sep 09 11:29:15 AM UTC 24 Sep 09 11:29:43 AM UTC 24 3419124109 ps
T428 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.2593126500 Sep 09 11:29:33 AM UTC 24 Sep 09 11:29:46 AM UTC 24 23164959 ps
T88 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_rw.1556640986 Sep 09 11:29:39 AM UTC 24 Sep 09 11:29:46 AM UTC 24 171706578 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.4116763293 Sep 09 11:29:21 AM UTC 24 Sep 09 11:29:48 AM UTC 24 2166198522 ps
T123 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.3524493725 Sep 09 11:29:42 AM UTC 24 Sep 09 11:29:48 AM UTC 24 3602276992 ps
T119 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_cfg_cmd.448117765 Sep 09 11:29:40 AM UTC 24 Sep 09 11:29:48 AM UTC 24 218471597 ps
T429 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_alert_test.2103503362 Sep 09 11:29:47 AM UTC 24 Sep 09 11:29:49 AM UTC 24 14141928 ps
T120 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_cfg_cmd.1671860891 Sep 09 11:30:16 AM UTC 24 Sep 09 11:30:20 AM UTC 24 107116244 ps
T430 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_csb_read.1266134636 Sep 09 11:29:47 AM UTC 24 Sep 09 11:29:49 AM UTC 24 21969653 ps
T121 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.2277035806 Sep 09 11:29:33 AM UTC 24 Sep 09 11:29:49 AM UTC 24 280551596 ps
T431 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.1449244177 Sep 09 11:29:48 AM UTC 24 Sep 09 11:29:50 AM UTC 24 10949332 ps
T182 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode.3855400036 Sep 09 11:29:40 AM UTC 24 Sep 09 11:29:50 AM UTC 24 178662594 ps
T134 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_intercept.2518823842 Sep 09 11:30:15 AM UTC 24 Sep 09 11:30:24 AM UTC 24 680424902 ps
T432 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.3555481388 Sep 09 11:29:39 AM UTC 24 Sep 09 11:29:51 AM UTC 24 33143974 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_upload.898364968 Sep 09 11:29:19 AM UTC 24 Sep 09 11:29:51 AM UTC 24 18385973393 ps
T433 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_all.2471524044 Sep 09 11:29:49 AM UTC 24 Sep 09 11:29:51 AM UTC 24 49860350 ps
T434 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.2202199490 Sep 09 11:29:49 AM UTC 24 Sep 09 11:29:51 AM UTC 24 36946772 ps
T223 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode.3591740874 Sep 09 11:29:32 AM UTC 24 Sep 09 11:29:52 AM UTC 24 409594362 ps
T291 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_mailbox.310308067 Sep 09 11:29:25 AM UTC 24 Sep 09 11:29:52 AM UTC 24 317272206 ps
T406 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_rw.2921660364 Sep 09 11:29:50 AM UTC 24 Sep 09 11:29:53 AM UTC 24 137350694 ps
T217 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_upload.1721518124 Sep 09 11:29:40 AM UTC 24 Sep 09 11:29:53 AM UTC 24 2305183047 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_all.2370761995 Sep 09 11:29:43 AM UTC 24 Sep 09 11:29:54 AM UTC 24 8021296115 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.1940364847 Sep 09 11:29:40 AM UTC 24 Sep 09 11:29:54 AM UTC 24 2095903623 ps
T435 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.3385862117 Sep 09 11:29:50 AM UTC 24 Sep 09 11:29:54 AM UTC 24 106610493 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.3864060962 Sep 09 11:29:10 AM UTC 24 Sep 09 11:29:55 AM UTC 24 1895804113 ps
T436 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_all.3268672686 Sep 09 11:29:53 AM UTC 24 Sep 09 11:29:55 AM UTC 24 26396387 ps
T70 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_intercept.2787726822 Sep 09 11:29:25 AM UTC 24 Sep 09 11:29:55 AM UTC 24 1152075981 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.1288051972 Sep 09 11:29:40 AM UTC 24 Sep 09 11:29:56 AM UTC 24 5084501038 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.781716996 Sep 09 11:29:31 AM UTC 24 Sep 09 11:29:56 AM UTC 24 13101942347 ps
T437 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_alert_test.3150200828 Sep 09 11:29:54 AM UTC 24 Sep 09 11:29:56 AM UTC 24 24656273 ps
T72 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_mailbox.3888003030 Sep 09 11:29:52 AM UTC 24 Sep 09 11:29:57 AM UTC 24 1777667718 ps
T438 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_alert_test.373890328 Sep 09 11:30:22 AM UTC 24 Sep 09 11:30:24 AM UTC 24 14926505 ps
T439 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_csb_read.3476992429 Sep 09 11:29:55 AM UTC 24 Sep 09 11:29:57 AM UTC 24 34760582 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.2342538688 Sep 09 11:29:50 AM UTC 24 Sep 09 11:29:58 AM UTC 24 3604069844 ps
T74 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.2111372823 Sep 09 11:29:57 AM UTC 24 Sep 09 11:29:59 AM UTC 24 14691957 ps
T75 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.2042629336 Sep 09 11:30:12 AM UTC 24 Sep 09 11:30:18 AM UTC 24 481026077 ps
T440 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.4052634261 Sep 09 11:29:38 AM UTC 24 Sep 09 11:30:00 AM UTC 24 7137873569 ps
T441 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode.3783528002 Sep 09 11:29:52 AM UTC 24 Sep 09 11:30:01 AM UTC 24 2112626859 ps
T221 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.183353585 Sep 09 11:29:25 AM UTC 24 Sep 09 11:30:01 AM UTC 24 29688969926 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.474331496 Sep 09 11:29:25 AM UTC 24 Sep 09 11:30:01 AM UTC 24 3689996345 ps
T303 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_cfg_cmd.767572253 Sep 09 11:29:52 AM UTC 24 Sep 09 11:30:01 AM UTC 24 563977315 ps
T405 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_all.2257746512 Sep 09 11:29:38 AM UTC 24 Sep 09 11:30:03 AM UTC 24 5123888878 ps
T219 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_intercept.3865834156 Sep 09 11:29:57 AM UTC 24 Sep 09 11:30:03 AM UTC 24 184392816 ps
T442 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.3084603335 Sep 09 11:29:53 AM UTC 24 Sep 09 11:30:03 AM UTC 24 1551178342 ps
T122 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_cfg_cmd.544441975 Sep 09 11:29:58 AM UTC 24 Sep 09 11:30:03 AM UTC 24 84780261 ps
T124 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_intercept.2670637672 Sep 09 11:29:40 AM UTC 24 Sep 09 11:30:04 AM UTC 24 6541241827 ps
T208 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_upload.1274553962 Sep 09 11:29:58 AM UTC 24 Sep 09 11:30:04 AM UTC 24 445452267 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_upload.2644748935 Sep 09 11:29:52 AM UTC 24 Sep 09 11:30:05 AM UTC 24 1480073348 ps
T84 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_stress_all.2645931852 Sep 09 11:30:03 AM UTC 24 Sep 09 11:30:05 AM UTC 24 239534619 ps
T412 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_rw.4149078647 Sep 09 11:29:57 AM UTC 24 Sep 09 11:30:05 AM UTC 24 996302135 ps
T249 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_intercept.465871787 Sep 09 11:29:50 AM UTC 24 Sep 09 11:30:06 AM UTC 24 2345366113 ps
T403 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_all.2670555854 Sep 09 11:29:30 AM UTC 24 Sep 09 11:30:06 AM UTC 24 15009068524 ps
T443 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_alert_test.1372368241 Sep 09 11:30:04 AM UTC 24 Sep 09 11:30:06 AM UTC 24 15539710 ps
T135 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_mailbox.1267134911 Sep 09 11:28:46 AM UTC 24 Sep 09 11:30:25 AM UTC 24 12390594490 ps
T444 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_csb_read.3283995250 Sep 09 11:30:04 AM UTC 24 Sep 09 11:30:06 AM UTC 24 71044198 ps
T445 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.1702612812 Sep 09 11:30:05 AM UTC 24 Sep 09 11:30:08 AM UTC 24 41428986 ps
T446 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_rw.2285723304 Sep 09 11:30:05 AM UTC 24 Sep 09 11:30:08 AM UTC 24 84655815 ps
T85 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.1939795601 Sep 09 11:28:50 AM UTC 24 Sep 09 11:30:08 AM UTC 24 9020644966 ps
T240 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode.1861869238 Sep 09 11:29:59 AM UTC 24 Sep 09 11:30:09 AM UTC 24 301330859 ps
T404 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_all.4220965204 Sep 09 11:28:59 AM UTC 24 Sep 09 11:30:09 AM UTC 24 2374863019 ps
T86 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_all.865552210 Sep 09 11:28:56 AM UTC 24 Sep 09 11:30:09 AM UTC 24 2506171684 ps
T447 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.3318989327 Sep 09 11:30:00 AM UTC 24 Sep 09 11:30:11 AM UTC 24 3569820840 ps
T448 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.656423822 Sep 09 11:30:06 AM UTC 24 Sep 09 11:30:11 AM UTC 24 158075742 ps
T327 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_upload.716999038 Sep 09 11:30:30 AM UTC 24 Sep 09 11:30:34 AM UTC 24 83553098 ps
T449 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.311657896 Sep 09 11:29:55 AM UTC 24 Sep 09 11:30:11 AM UTC 24 4096345320 ps
T450 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_upload.2713512305 Sep 09 11:30:07 AM UTC 24 Sep 09 11:30:12 AM UTC 24 43579785 ps
T451 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_alert_test.3082008031 Sep 09 11:30:10 AM UTC 24 Sep 09 11:30:13 AM UTC 24 34140997 ps
T302 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_cfg_cmd.1275363642 Sep 09 11:30:07 AM UTC 24 Sep 09 11:30:13 AM UTC 24 163650159 ps
T452 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_csb_read.5309820 Sep 09 11:30:25 AM UTC 24 Sep 09 11:30:27 AM UTC 24 38910601 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.1858501615 Sep 09 11:29:21 AM UTC 24 Sep 09 11:30:13 AM UTC 24 21033451765 ps
T453 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_csb_read.824695170 Sep 09 11:30:11 AM UTC 24 Sep 09 11:30:13 AM UTC 24 66132423 ps
T454 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.1997412206 Sep 09 11:30:09 AM UTC 24 Sep 09 11:30:14 AM UTC 24 266644128 ps
T455 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.4201183533 Sep 09 11:30:05 AM UTC 24 Sep 09 11:30:15 AM UTC 24 18634997387 ps
T456 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_rw.645942675 Sep 09 11:30:14 AM UTC 24 Sep 09 11:30:16 AM UTC 24 65273758 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.4069713291 Sep 09 11:29:57 AM UTC 24 Sep 09 11:30:16 AM UTC 24 20974120527 ps
T457 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.3654687444 Sep 09 11:30:14 AM UTC 24 Sep 09 11:30:16 AM UTC 24 44994184 ps
T104 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.222577657 Sep 09 11:29:30 AM UTC 24 Sep 09 11:30:16 AM UTC 24 9077076031 ps
T113 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_all.451894399 Sep 09 11:30:12 AM UTC 24 Sep 09 11:30:19 AM UTC 24 1671459521 ps
T308 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.97981567 Sep 09 11:30:14 AM UTC 24 Sep 09 11:30:20 AM UTC 24 1108916766 ps
T222 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.3340366429 Sep 09 11:29:57 AM UTC 24 Sep 09 11:30:24 AM UTC 24 22543490699 ps
T242 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.583109339 Sep 09 11:30:06 AM UTC 24 Sep 09 11:30:26 AM UTC 24 12715607634 ps
T114 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.1824943783 Sep 09 11:29:53 AM UTC 24 Sep 09 11:30:28 AM UTC 24 2646421269 ps
T458 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.3511748537 Sep 09 11:30:25 AM UTC 24 Sep 09 11:30:28 AM UTC 24 721987685 ps
T459 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.1790117829 Sep 09 11:30:27 AM UTC 24 Sep 09 11:30:29 AM UTC 24 24190370 ps
T215 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.1524024388 Sep 09 11:30:08 AM UTC 24 Sep 09 11:30:30 AM UTC 24 10666834948 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.3967087970 Sep 09 11:30:28 AM UTC 24 Sep 09 11:30:33 AM UTC 24 179246166 ps
T396 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_all.4129763793 Sep 09 11:30:05 AM UTC 24 Sep 09 11:30:35 AM UTC 24 5655678062 ps
T344 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_mailbox.2197156147 Sep 09 11:30:15 AM UTC 24 Sep 09 11:30:35 AM UTC 24 14088046621 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_upload.2396132828 Sep 09 11:30:15 AM UTC 24 Sep 09 11:30:35 AM UTC 24 21314955928 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode.3757836168 Sep 09 11:30:17 AM UTC 24 Sep 09 11:30:37 AM UTC 24 444538881 ps
T136 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.2214023100 Sep 09 11:30:17 AM UTC 24 Sep 09 11:30:37 AM UTC 24 11069502452 ps
T137 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_rw.3627234930 Sep 09 11:30:27 AM UTC 24 Sep 09 11:30:37 AM UTC 24 184863732 ps
T61 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.1613463114 Sep 09 11:29:29 AM UTC 24 Sep 09 11:30:40 AM UTC 24 9404503521 ps
T162 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_alert_test.16285438 Sep 09 11:30:38 AM UTC 24 Sep 09 11:30:40 AM UTC 24 11898926 ps
T163 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_intercept.2275706898 Sep 09 11:30:07 AM UTC 24 Sep 09 11:30:40 AM UTC 24 8137295041 ps
T164 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_all.1989546213 Sep 09 11:29:57 AM UTC 24 Sep 09 11:30:40 AM UTC 24 3110824609 ps
T165 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_all.3774312531 Sep 09 11:29:21 AM UTC 24 Sep 09 11:30:40 AM UTC 24 9410520288 ps
T166 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_intercept.540329488 Sep 09 11:30:29 AM UTC 24 Sep 09 11:30:41 AM UTC 24 427234275 ps
T167 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_mailbox.4220159171 Sep 09 11:29:40 AM UTC 24 Sep 09 11:30:42 AM UTC 24 29294222802 ps
T168 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.1323684705 Sep 09 11:30:35 AM UTC 24 Sep 09 11:30:42 AM UTC 24 103093463 ps
T169 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_mode.2331501874 Sep 09 11:31:11 AM UTC 24 Sep 09 11:31:19 AM UTC 24 113710345 ps
T170 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.1960864404 Sep 09 11:29:59 AM UTC 24 Sep 09 11:30:43 AM UTC 24 4763951632 ps
T460 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_csb_read.1033779909 Sep 09 11:30:41 AM UTC 24 Sep 09 11:30:43 AM UTC 24 16379414 ps
T461 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.4025091241 Sep 09 11:30:41 AM UTC 24 Sep 09 11:30:43 AM UTC 24 49116440 ps
T409 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_all.2371695737 Sep 09 11:30:26 AM UTC 24 Sep 09 11:30:43 AM UTC 24 976796909 ps
T413 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_rw.3377438717 Sep 09 11:30:42 AM UTC 24 Sep 09 11:30:44 AM UTC 24 24560815 ps
T323 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_cfg_cmd.3914019269 Sep 09 11:30:31 AM UTC 24 Sep 09 11:30:44 AM UTC 24 1756176271 ps
T408 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm.3179482526 Sep 09 11:30:36 AM UTC 24 Sep 09 11:30:45 AM UTC 24 4019466443 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.4035529638 Sep 09 11:29:42 AM UTC 24 Sep 09 11:30:46 AM UTC 24 7985579751 ps
T462 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode.3107524138 Sep 09 11:30:34 AM UTC 24 Sep 09 11:30:46 AM UTC 24 686072208 ps
T463 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode.22240817 Sep 09 11:30:44 AM UTC 24 Sep 09 11:30:49 AM UTC 24 36557303 ps
T464 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.3446573311 Sep 09 11:30:41 AM UTC 24 Sep 09 11:30:51 AM UTC 24 6036203099 ps
T398 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_all.763120972 Sep 09 11:30:41 AM UTC 24 Sep 09 11:30:51 AM UTC 24 6054469097 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode_ignore_cmds.601593808 Sep 09 11:30:35 AM UTC 24 Sep 09 11:30:52 AM UTC 24 1898551319 ps
T410 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.2550082482 Sep 09 11:30:47 AM UTC 24 Sep 09 11:30:53 AM UTC 24 380867516 ps
T125 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.2383463218 Sep 09 11:29:26 AM UTC 24 Sep 09 11:30:53 AM UTC 24 33922614179 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.3744441871 Sep 09 11:30:28 AM UTC 24 Sep 09 11:30:54 AM UTC 24 41120478268 ps
T465 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_alert_test.1694210262 Sep 09 11:30:52 AM UTC 24 Sep 09 11:30:54 AM UTC 24 44231327 ps
T466 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_csb_read.340996460 Sep 09 11:30:52 AM UTC 24 Sep 09 11:30:54 AM UTC 24 53313362 ps
T331 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.1397866557 Sep 09 11:30:43 AM UTC 24 Sep 09 11:30:54 AM UTC 24 9555912748 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_all.2152509247 Sep 09 11:29:27 AM UTC 24 Sep 09 11:30:55 AM UTC 24 4014657478 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.4186173484 Sep 09 11:29:53 AM UTC 24 Sep 09 11:30:57 AM UTC 24 2758289245 ps
T467 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.2671688506 Sep 09 11:30:54 AM UTC 24 Sep 09 11:30:57 AM UTC 24 98328058 ps
T248 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.1076402194 Sep 09 11:30:17 AM UTC 24 Sep 09 11:30:57 AM UTC 24 3910643132 ps
T468 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.1158385439 Sep 09 11:30:54 AM UTC 24 Sep 09 11:30:57 AM UTC 24 389383339 ps
T469 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_rw.2724207046 Sep 09 11:30:55 AM UTC 24 Sep 09 11:30:58 AM UTC 24 16473795 ps
T307 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.3501284729 Sep 09 11:30:43 AM UTC 24 Sep 09 11:30:58 AM UTC 24 5619414948 ps
T470 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.976967774 Sep 09 11:30:46 AM UTC 24 Sep 09 11:30:59 AM UTC 24 1364695380 ps
T339 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.3646561156 Sep 09 11:30:15 AM UTC 24 Sep 09 11:30:59 AM UTC 24 54450246236 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_mailbox.2447600614 Sep 09 11:30:07 AM UTC 24 Sep 09 11:31:01 AM UTC 24 25937900198 ps
T338 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.986918680 Sep 09 11:30:56 AM UTC 24 Sep 09 11:31:02 AM UTC 24 83021465 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_mailbox.384860169 Sep 09 11:30:57 AM UTC 24 Sep 09 11:31:03 AM UTC 24 523202427 ps
T309 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_cfg_cmd.1806517271 Sep 09 11:30:58 AM UTC 24 Sep 09 11:31:03 AM UTC 24 161566989 ps
T253 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_intercept.648636453 Sep 09 11:30:56 AM UTC 24 Sep 09 11:31:04 AM UTC 24 2727918232 ps
T471 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_alert_test.248717218 Sep 09 11:31:02 AM UTC 24 Sep 09 11:31:05 AM UTC 24 44624888 ps
T218 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_mailbox.1178387684 Sep 09 11:30:29 AM UTC 24 Sep 09 11:31:05 AM UTC 24 7109890765 ps
T472 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_read_buffer_direct.1892043185 Sep 09 11:30:59 AM UTC 24 Sep 09 11:31:06 AM UTC 24 176331911 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_stress_all.1804892222 Sep 09 11:31:18 AM UTC 24 Sep 09 11:31:20 AM UTC 24 36822312 ps
T473 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_csb_read.766741510 Sep 09 11:31:05 AM UTC 24 Sep 09 11:31:07 AM UTC 24 15463444 ps
T300 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_intercept.742925031 Sep 09 11:30:44 AM UTC 24 Sep 09 11:31:07 AM UTC 24 20205243108 ps
T474 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode.942924262 Sep 09 11:30:58 AM UTC 24 Sep 09 11:31:08 AM UTC 24 1465018268 ps
T475 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_sts_read.4018141972 Sep 09 11:31:06 AM UTC 24 Sep 09 11:31:08 AM UTC 24 11854564 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_stress_all.1537550986 Sep 09 11:29:37 AM UTC 24 Sep 09 11:31:10 AM UTC 24 11504008523 ps
T476 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_all.1322990263 Sep 09 11:31:06 AM UTC 24 Sep 09 11:31:10 AM UTC 24 402623201 ps
T397 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_all.2843029662 Sep 09 11:30:54 AM UTC 24 Sep 09 11:31:12 AM UTC 24 2531957917 ps
T315 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_pass_cmd_filtering.1522872685 Sep 09 11:31:07 AM UTC 24 Sep 09 11:31:12 AM UTC 24 92675182 ps
T477 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_mailbox.2650557484 Sep 09 11:29:58 AM UTC 24 Sep 09 11:31:14 AM UTC 24 40845435235 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_cmd_filtering.606691632 Sep 09 11:30:56 AM UTC 24 Sep 09 11:31:15 AM UTC 24 1967521839 ps
T478 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_rw.1475644168 Sep 09 11:31:07 AM UTC 24 Sep 09 11:31:16 AM UTC 24 250683383 ps
T314 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_intercept.894370419 Sep 09 11:31:08 AM UTC 24 Sep 09 11:31:17 AM UTC 24 556099011 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.3386141909 Sep 09 11:29:10 AM UTC 24 Sep 09 11:31:18 AM UTC 24 55340714012 ps
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T479 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_read_buffer_direct.2394311965 Sep 09 11:31:13 AM UTC 24 Sep 09 11:31:19 AM UTC 24 966269376 ps
T480 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_read_hw_reg.3443423042 Sep 09 11:31:06 AM UTC 24 Sep 09 11:31:21 AM UTC 24 2105605364 ps
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T481 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_alert_test.1491975523 Sep 09 11:31:19 AM UTC 24 Sep 09 11:31:21 AM UTC 24 48521364 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_upload.3360941867 Sep 09 11:32:00 AM UTC 24 Sep 09 11:32:07 AM UTC 24 1471587206 ps
T482 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_csb_read.3854655587 Sep 09 11:31:19 AM UTC 24 Sep 09 11:31:22 AM UTC 24 45707335 ps
T483 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_sts_read.4076317354 Sep 09 11:31:21 AM UTC 24 Sep 09 11:31:24 AM UTC 24 22960125 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_upload.2040061353 Sep 09 11:31:09 AM UTC 24 Sep 09 11:31:24 AM UTC 24 2192702753 ps
T322 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_upload.2674641103 Sep 09 11:30:58 AM UTC 24 Sep 09 11:31:24 AM UTC 24 9138625261 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_upload.655140847 Sep 09 11:30:44 AM UTC 24 Sep 09 11:31:24 AM UTC 24 25391040025 ps
T310 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_mailbox.1420830668 Sep 09 11:31:08 AM UTC 24 Sep 09 11:31:24 AM UTC 24 811167161 ps
T320 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_cfg_cmd.89921548 Sep 09 11:31:10 AM UTC 24 Sep 09 11:31:24 AM UTC 24 3565891621 ps
T484 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_read_hw_reg.136120510 Sep 09 11:31:20 AM UTC 24 Sep 09 11:31:24 AM UTC 24 324207682 ps
T485 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_rw.1640151057 Sep 09 11:31:22 AM UTC 24 Sep 09 11:31:25 AM UTC 24 87535796 ps
T486 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_intercept.597255084 Sep 09 11:31:24 AM UTC 24 Sep 09 11:31:28 AM UTC 24 58193972 ps
T487 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_all.2756233242 Sep 09 11:31:15 AM UTC 24 Sep 09 11:31:28 AM UTC 24 4265034595 ps
T261 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_pass_addr_payload_swap.3562195756 Sep 09 11:31:08 AM UTC 24 Sep 09 11:31:29 AM UTC 24 10790707055 ps
T488 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_cfg_cmd.2249169674 Sep 09 11:30:44 AM UTC 24 Sep 09 11:31:30 AM UTC 24 14999034235 ps
T489 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_cfg_cmd.2497444637 Sep 09 11:31:25 AM UTC 24 Sep 09 11:31:31 AM UTC 24 924407473 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode.2272554128 Sep 09 11:31:25 AM UTC 24 Sep 09 11:31:31 AM UTC 24 93649076 ps
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