Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	36035	1			T1	6		T5	2		T7	11
auto[SpiFlashAddrCfg]	7686	1			T7	3		T8	1		T10	2
auto[SpiFlashAddr3b]	9305	1			T3	6		T7	4		T10	2
auto[SpiFlashAddr4b]	7614	1			T1	2		T7	2		T8	6

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34414

1

T1

8

T3

6

T5

2

auto[1]

26226

1

T7

4

T10

8

T45

20

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31799

1

T1

2

T3

6

T5

2

auto[1]

28841

1

T1

6

T7

5

T8

4

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	40695	1			T1	6		T3	2		T5	2
values[1]	1138	1			T7	2		T10	2		T45	1
values[2]	1451	1			T63	2		T45	2		T62	4
values[3]	1435	1			T3	2		T7	1		T63	4
values[4]	1501	1			T10	2		T47	2		T87	2
values[5]	1515	1			T7	1		T24	4		T51	2
values[6]	1494	1			T12	4		T207	8		T52	2
values[7]	1518	1			T10	2		T52	4		T53	2
values[8]	9893	1			T1	2		T3	2		T7	5

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31643

1

T1

8

T3

6

T5

2

auto[1]

28997

1

T7

20

T8

7

T47

3

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

57277

1

T1

8

T3

6

T5

2

write

3363

1

T12

4

T37

2

T24

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19489

1

T3

4

T5

2

T7

13

valids[0x1]

41151

1

T1

8

T3

2

T7

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1558	1			T1	2		T7	1		T51	4
internal_process_ops[0x5a]	1574	1			T7	1		T87	2		T24	2
internal_process_ops[0x05]	22038	1			T1	2		T7	1		T10	2
internal_process_ops[0x35]	1555	1			T1	2		T7	1		T87	2
internal_process_ops[0x15]	1511	1			T7	1		T87	2		T24	2
internal_process_ops[0x03]	1029	1			T3	2		T8	1		T132	4
internal_process_ops[0x0b]	1076	1			T1	2		T8	3		T10	2
internal_process_ops[0x3b]	1086	1			T7	1		T10	2		T11	2
internal_process_ops[0x6b]	1067	1			T8	1		T51	2		T207	2
internal_process_ops[0xbb]	1054	1			T12	2		T50	2		T47	1
internal_process_ops[0xeb]	1094	1			T8	2		T11	2		T59	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58987

1

T1

8

T3

6

T5

2

auto[1]

1653

1

T45

2

T43

1

T53

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58151

1

T1

8

T3

6

T5

2

auto[1]

2489

1

T37

2

T45

6

T43

2

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10154

1

T1

6

T5

2

T9

6

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6877

1

T10

2

T58

2

T59

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2158

1

T11

4

T12

6

T63

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1846

1

T10

2

T58

4

T59

10

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2629

1

T3

6

T11

2

T50

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2297

1

T10

2

T59

10

T53

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2153

1

T1

2

T12

2

T63

8

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1887

1

T10

2

T58

6

T55

8

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

105

1

T208

4

T57

2

T171

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

98

1

T55

1

T49

1

T66

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

96

1

T66

2

T67

1

T68

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

106

1

T66

3

T67

1

T68

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

115

1

T37

2

T52

2

T55

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

85

1

T53

2

T66

2

T68

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

101

1

T66

2

T209

2

T210

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

105

1

T170

1

T64

1

T49

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

136

1

T12

4

T54

6

T55

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

100

1

T61

3

T64

1

T66

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

82

1

T66

1

T171

1

T211

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

103

1

T69

5

T212

4

T213

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

113

1

T24

2

T62

2

T170

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

82

1

T61

1

T67

1

T68

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

118

1

T61

2

T66

6

T67

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

97

1

T60

2

T61

1

T171

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10975

1

T7

10

T45

7

T43

18

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7205

1

T7

1

T45

5

T43

2

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1444

1

T7

2

T8

1

T47

3

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1381

1

T7

1

T45

1

T43

3

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1797

1

T7

3

T45

2

T180

2

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1768

1

T7

1

T45

9

T85

14

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1395

1

T7

1

T8

6

T45

2

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1311

1

T7

1

T45

1

T85

16

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

118

1

T85

1

T114

2

T38

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

112

1

T85

1

T86

8

T48

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

94

1

T86

4

T38

2

T214

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

95

1

T45

2

T86

1

T114

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

119

1

T85

2

T114

3

T38

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

102

1

T43

1

T86

2

T48

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

106

1

T85

3

T86

2

T125

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

124

1

T86

2

T125

3

T206

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

86

1

T86

3

T165

2

T214

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

104

1

T85

1

T86

3

T48

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

101

1

T45

2

T85

1

T114

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

102

1

T86

2

T215

1

T165

5

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

122

1

T43

1

T85

1

T86

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

112

1

T86

3

T125

1

T216

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

98

1

T85

1

T86

2

T38

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

126

1

T85

3

T165

1

T125

3

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4064	1			T5	2		T9	6		T12	4
auto[0]	values[0]	valids[0x1]	15930	1			T1	6		T3	2		T10	2
auto[0]	values[1]	valids[0x1]	627	1			T10	2		T52	2		T55	3
auto[0]	values[2]	valids[0x0]	569	1			T62	4		T217	4		T55	2
auto[0]	values[2]	valids[0x1]	293	1			T63	2		T61	3		T218	4
auto[0]	values[3]	valids[0x0]	537	1			T3	2		T63	4		T61	4
auto[0]	values[3]	valids[0x1]	315	1			T58	2		T56	2		T219	4
auto[0]	values[4]	valids[0x0]	550	1			T132	6		T59	2		T53	1
auto[0]	values[4]	valids[0x1]	324	1			T10	2		T87	2		T53	1
auto[0]	values[5]	valids[0x0]	566	1			T51	2		T207	2		T55	6
auto[0]	values[5]	valids[0x1]	308	1			T24	4		T220	2		T59	2
auto[0]	values[6]	valids[0x0]	613	1			T12	4		T207	4		T52	2
auto[0]	values[6]	valids[0x1]	289	1			T207	4		T221	2		T61	1
auto[0]	values[7]	valids[0x0]	571	1			T10	2		T52	2		T53	2
auto[0]	values[7]	valids[0x1]	322	1			T52	2		T56	2		T222	4
auto[0]	values[8]	valids[0x0]	3662	1			T3	2		T11	4		T50	2
auto[0]	values[8]	valids[0x1]	2103	1			T1	2		T11	2		T63	4
auto[1]	values[0]	valids[0x0]	3804	1			T7	7		T45	8		T43	9
auto[1]	values[0]	valids[0x1]	16897	1			T7	4		T8	3		T45	10
auto[1]	values[1]	valids[0x1]	511	1			T7	2		T45	1		T43	1
auto[1]	values[2]	valids[0x0]	343	1			T85	4		T86	3		T48	1
auto[1]	values[2]	valids[0x1]	246	1			T45	2		T85	2		T86	5
auto[1]	values[3]	valids[0x0]	334	1			T7	1		T47	1		T85	1
auto[1]	values[3]	valids[0x1]	249	1			T223	1		T86	1		T48	2
auto[1]	values[4]	valids[0x0]	375	1			T47	2		T45	1		T85	1
auto[1]	values[4]	valids[0x1]	252	1			T45	1		T85	2		T86	5
auto[1]	values[5]	valids[0x0]	374	1			T7	1		T45	1		T180	2
auto[1]	values[5]	valids[0x1]	267	1			T86	1		T48	3		T165	2
auto[1]	values[6]	valids[0x0]	313	1			T85	6		T86	1		T215	1
auto[1]	values[6]	valids[0x1]	279	1			T85	4		T86	8		T48	3
auto[1]	values[7]	valids[0x0]	378	1			T85	4		T86	5		T48	4
auto[1]	values[7]	valids[0x1]	247	1			T85	2		T86	4		T165	1
auto[1]	values[8]	valids[0x0]	2436	1			T7	4		T8	1		T45	11
auto[1]	values[8]	valids[0x1]	1692	1			T7	1		T8	3		T45	5