Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3352191

1

T1

206

T3

1

T4

1

auto[1]

29741

1

T37

34

T45

55

T43

9

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

947093

1

T1

206

T3

1

T4

1

auto[1]

2434839

1

T7

2151

T12

512

T76

256

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	613468	1			T1	24		T3	1		T4	1
auto[524288:1048575]	383601	1			T8	179		T9	1		T78	12
auto[1048576:1572863]	396893	1			T1	47		T8	169		T76	254
auto[1572864:2097151]	420226	1			T1	26		T9	1		T78	144
auto[2097152:2621439]	398201	1			T1	1		T50	156		T47	3
auto[2621440:3145727]	421382	1			T1	51		T5	273		T8	97
auto[3145728:3670015]	353180	1			T1	47		T5	3		T9	187
auto[3670016:4194303]	394981	1			T1	10		T7	1		T8	50

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2468698

1

T1

19

T3

1

T4

1

auto[1]

913234

1

T1

187

T5

293

T8

485

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2858277

1

T1

206

T3

1

T4

1

auto[1]

523655

1

T5

204

T7

2147

T35

8

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	202161	1			T1	24		T3	1		T4	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	356102	1			T7	6		T12	512		T37	2
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	72744	1			T8	179		T9	1		T78	12
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	233880	1			T85	255		T114	1		T165	3072
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	123119	1			T1	47		T8	169		T76	111
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	210703	1			T76	143		T45	1350		T85	3638
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	112881	1			T1	26		T9	1		T78	144
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	225201	1			T55	645		T86	2		T48	145
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	94197	1			T1	1		T50	156		T47	3
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	244838	1			T53	512		T86	3160		T104	2166
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	131692	1			T1	51		T5	72		T8	97
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	200494	1			T45	229		T53	1		T55	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	92943	1			T1	47		T9	187		T11	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	195077	1			T76	113		T45	653		T86	257
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	96653	1			T1	10		T7	1		T8	50
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	242238	1			T134	6		T85	4		T86	3596
auto[0]	auto[1]	auto[0:524287]	auto[0]	2997	1			T7	2		T35	1		T43	3
auto[0]	auto[1]	auto[0:524287]	auto[1]	47818	1			T7	2145		T43	45		T86	1282
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1376	1			T53	2		T86	1		T125	8
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	71157	1			T53	1		T86	129		T125	5
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	3068	1			T120	3		T85	12		T302	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	56372	1			T85	128		T215	512		T38	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	2216	1			T61	5		T165	8		T125	71
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	77408	1			T61	1982		T165	2093		T125	1026
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	3354	1			T165	2		T125	15		T66	3
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	51761	1			T48	256		T165	1		T38	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1575	1			T5	201		T85	8		T86	3
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	83784	1			T48	256		T61	5		T165	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1512	1			T5	3		T35	7		T48	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	60635	1			T165	128		T125	3249		T66	2802
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	611	1			T43	2		T85	18		T86	9
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	51624	1			T43	1412		T85	256		T86	27
auto[1]	auto[0]	auto[0:524287]	auto[0]	491	1			T37	2		T62	2		T55	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	3239	1			T37	32		T62	12		T57	60
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	341	1			T85	6		T114	1		T125	6
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2587	1			T114	4		T66	8		T38	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	386	1			T45	5		T85	8		T114	3
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2636	1			T114	4		T66	9		T38	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	342	1			T45	5		T55	2		T86	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1531	1			T55	12		T86	12		T66	59
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	468	1			T86	5		T61	1		T165	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2693	1			T86	54		T61	3		T165	13
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	408	1			T45	3		T53	1		T55	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2852	1			T45	31		T53	32		T55	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	382	1			T45	6		T85	5		T86	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2048	1			T86	38		T114	14		T165	27
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	372	1			T45	5		T85	19		T86	4
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2578	1			T85	7		T86	152		T206	6
auto[1]	auto[1]	auto[0:524287]	auto[0]	123	1			T43	2		T86	2		T125	6
auto[1]	auto[1]	auto[0:524287]	auto[1]	537	1			T43	7		T86	43		T214	34
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	118	1			T53	1		T86	1		T66	2
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	1398	1			T53	37		T86	13		T66	66
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	112	1			T38	2		T210	1		T254	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	497	1			T38	8		T210	51		T254	4
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	77	1			T61	3		T165	4		T125	3
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	570	1			T61	19		T165	19		T66	60
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	86	1			T165	1		T38	2		T171	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	804	1			T165	13		T38	15		T171	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	99	1			T165	1		T125	17		T66	3
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	478	1			T165	9		T66	82		T216	11
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	120	1			T248	4		T69	3		T270	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	463	1			T69	5		T270	35		T107	38
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	69	1			T86	2		T48	1		T165	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	836	1			T86	30		T48	3		T165	6

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1933896	1			T1	19		T3	1		T4	1
auto[0]	auto[0]	auto[1]	901027	1			T1	187		T5	160		T8	485
auto[0]	auto[1]	auto[0]	505828	1			T5	71		T7	2147		T35	3
auto[0]	auto[1]	auto[1]	11440	1			T5	133		T35	5		T303	1226
auto[1]	auto[0]	auto[0]	22723	1			T37	34		T45	49		T62	12
auto[1]	auto[0]	auto[1]	631	1			T45	6		T62	2		T53	1
auto[1]	auto[1]	auto[0]	6251	1			T43	9		T53	38		T86	91
auto[1]	auto[1]	auto[1]	136	1			T165	2		T125	4		T248	1