Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2789752	1			T1	1		T2	1		T3	14
all_pins[1]	2789752	1			T1	1		T2	1		T3	14
all_pins[2]	2789752	1			T1	1		T2	1		T3	14
all_pins[3]	2789752	1			T1	1		T2	1		T3	14
all_pins[4]	2789752	1			T1	1		T2	1		T3	14
all_pins[5]	2789752	1			T1	1		T2	1		T3	14
all_pins[6]	2789752	1			T1	1		T2	1		T3	14
all_pins[7]	2789752	1			T1	1		T2	1		T3	14

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	22268784	1			T1	8		T2	8		T3	112
values[0x1]	49232	1			T15	64		T84	49		T33	47
transitions[0x0=>0x1]	48054	1			T15	51		T84	37		T33	31
transitions[0x1=>0x0]	48071	1			T15	52		T84	37		T33	32

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2789301	1			T1	1		T2	1		T3	14
all_pins[0]	values[0x1]	451	1			T15	7		T84	7		T33	6
all_pins[0]	transitions[0x0=>0x1]	394	1			T15	3		T84	6		T33	5
all_pins[0]	transitions[0x1=>0x0]	290	1			T15	11		T84	6		T33	1
all_pins[1]	values[0x0]	2789405	1			T1	1		T2	1		T3	14
all_pins[1]	values[0x1]	347	1			T15	15		T84	7		T33	2
all_pins[1]	transitions[0x0=>0x1]	307	1			T15	12		T84	6		T33	1
all_pins[1]	transitions[0x1=>0x0]	152	1			T15	3		T84	5		T33	3
all_pins[2]	values[0x0]	2789560	1			T1	1		T2	1		T3	14
all_pins[2]	values[0x1]	192	1			T15	6		T84	6		T33	4
all_pins[2]	transitions[0x0=>0x1]	150	1			T15	5		T84	6		T33	3
all_pins[2]	transitions[0x1=>0x0]	146	1			T15	6		T84	5		T33	5
all_pins[3]	values[0x0]	2789564	1			T1	1		T2	1		T3	14
all_pins[3]	values[0x1]	188	1			T15	7		T84	5		T33	6
all_pins[3]	transitions[0x0=>0x1]	146	1			T15	6		T84	1		T33	4
all_pins[3]	transitions[0x1=>0x0]	148	1			T15	3		T84	4		T33	3
all_pins[4]	values[0x0]	2789562	1			T1	1		T2	1		T3	14
all_pins[4]	values[0x1]	190	1			T15	4		T84	8		T33	5
all_pins[4]	transitions[0x0=>0x1]	152	1			T15	4		T84	7		T33	4
all_pins[4]	transitions[0x1=>0x0]	1054	1			T15	5		T84	2		T33	6
all_pins[5]	values[0x0]	2788660	1			T1	1		T2	1		T3	14
all_pins[5]	values[0x1]	1092	1			T15	5		T84	3		T33	7
all_pins[5]	transitions[0x0=>0x1]	247	1			T15	4		T84	1		T33	4
all_pins[5]	transitions[0x1=>0x0]	45737	1			T15	6		T84	6		T33	3
all_pins[6]	values[0x0]	2743170	1			T1	1		T2	1		T3	14
all_pins[6]	values[0x1]	46582	1			T15	7		T84	8		T33	6
all_pins[6]	transitions[0x0=>0x1]	46529	1			T15	6		T84	7		T33	3
all_pins[6]	transitions[0x1=>0x0]	137	1			T15	12		T84	4		T33	8
all_pins[7]	values[0x0]	2789562	1			T1	1		T2	1		T3	14
all_pins[7]	values[0x1]	190	1			T15	13		T84	5		T33	11
all_pins[7]	transitions[0x0=>0x1]	129	1			T15	11		T84	3		T33	7
all_pins[7]	transitions[0x1=>0x0]	407	1			T15	6		T84	5		T33	3