Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17928

1

T1

8

T3

6

T5

2

auto[1]

13715

1

T10

8

T58

12

T59

24

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3825	1			T11	6		T12	18		T76	2
values[1]	3853	1			T63	14		T35	12		T59	24
values[2]	3461	1			T87	6		T132	10		T304	4
values[3]	3944	1			T3	6		T10	8		T51	10
values[4]	4132	1			T5	2		T70	2		T302	16
values[5]	4059	1			T1	8		T24	12		T60	22
values[6]	4018	1			T9	6		T120	10		T134	8
values[7]	4351	1			T78	8		T220	2		T118	12

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3439	1			T5	2		T10	8		T87	6
values[1]	3835	1			T58	12		T217	8		T57	76
values[2]	3898	1			T76	2		T50	2		T220	2
values[3]	3854	1			T1	8		T119	6		T62	32
values[4]	4419	1			T3	6		T9	6		T78	8
values[5]	4286	1			T35	12		T52	20		T291	8
values[6]	4452	1			T11	6		T12	18		T63	14
values[7]	3460	1			T37	36		T241	12		T120	10

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	246	1			T171	14		T69	85		T201	12
auto[0]	values[0]	values[1]	348	1			T49	12		T68	9		T254	11
auto[0]	values[0]	values[2]	432	1			T76	2		T50	2		T54	20
auto[0]	values[0]	values[3]	170	1			T210	10		T305	12		T306	35
auto[0]	values[0]	values[4]	227	1			T307	16		T68	14		T199	12
auto[0]	values[0]	values[5]	248	1			T249	4		T171	10		T209	10
auto[0]	values[0]	values[6]	276	1			T11	6		T12	18		T171	12
auto[0]	values[0]	values[7]	142	1			T37	36		T241	12		T308	4
auto[0]	values[1]	values[0]	267	1			T208	20		T238	12		T298	14
auto[0]	values[1]	values[1]	275	1			T64	14		T309	8		T69	7
auto[0]	values[1]	values[2]	411	1			T66	77		T68	17		T69	11
auto[0]	values[1]	values[3]	323	1			T119	6		T62	32		T171	12
auto[0]	values[1]	values[4]	189	1			T122	18		T310	2		T211	12
auto[0]	values[1]	values[5]	214	1			T35	12		T219	6		T166	24
auto[0]	values[1]	values[6]	255	1			T63	14		T211	14		T293	6
auto[0]	values[1]	values[7]	291	1			T311	4		T209	5		T266	22
auto[0]	values[2]	values[0]	385	1			T87	6		T55	10		T68	15
auto[0]	values[2]	values[1]	249	1			T66	53		T68	19		T210	9
auto[0]	values[2]	values[2]	164	1			T210	12		T201	13		T294	10
auto[0]	values[2]	values[3]	190	1			T275	14		T251	12		T267	16
auto[0]	values[2]	values[4]	277	1			T132	10		T304	4		T66	4
auto[0]	values[2]	values[5]	241	1			T172	7		T312	12		T313	2
auto[0]	values[2]	values[6]	186	1			T286	10		T61	12		T314	10
auto[0]	values[2]	values[7]	235	1			T61	33		T289	7		T245	12
auto[0]	values[3]	values[0]	277	1			T254	18		T238	11		T297	11
auto[0]	values[3]	values[1]	213	1			T217	8		T315	4		T68	8
auto[0]	values[3]	values[2]	427	1			T209	9		T172	9		T316	6
auto[0]	values[3]	values[3]	264	1			T292	16		T317	4		T318	10
auto[0]	values[3]	values[4]	351	1			T3	6		T51	10		T221	22
auto[0]	values[3]	values[5]	261	1			T210	35		T172	12		T250	16
auto[0]	values[3]	values[6]	169	1			T244	12		T254	26		T238	9
auto[0]	values[3]	values[7]	274	1			T55	13		T66	27		T285	20
auto[0]	values[4]	values[0]	184	1			T5	2		T254	15		T201	11
auto[0]	values[4]	values[1]	268	1			T67	12		T319	6		T172	9
auto[0]	values[4]	values[2]	183	1			T320	4		T211	7		T69	10
auto[0]	values[4]	values[3]	400	1			T70	2		T167	4		T66	9
auto[0]	values[4]	values[4]	308	1			T61	9		T66	9		T209	44
auto[0]	values[4]	values[5]	373	1			T302	16		T66	74		T68	10
auto[0]	values[4]	values[6]	194	1			T170	13		T66	16		T209	10
auto[0]	values[4]	values[7]	315	1			T64	10		T248	14		T218	14
auto[0]	values[5]	values[0]	139	1			T209	10		T251	9		T247	7
auto[0]	values[5]	values[1]	255	1			T66	6		T68	15		T69	14
auto[0]	values[5]	values[2]	232	1			T282	47		T321	21		T210	14
auto[0]	values[5]	values[3]	259	1			T1	8		T171	10		T322	10
auto[0]	values[5]	values[4]	285	1			T24	12		T256	8		T288	42
auto[0]	values[5]	values[5]	233	1			T323	14		T267	14		T294	12
auto[0]	values[5]	values[6]	559	1			T163	12		T66	59		T268	76
auto[0]	values[5]	values[7]	203	1			T324	6		T325	22		T326	16
auto[0]	values[6]	values[0]	239	1			T68	12		T254	17		T312	9
auto[0]	values[6]	values[1]	256	1			T290	24		T288	11		T258	43
auto[0]	values[6]	values[2]	282	1			T135	4		T327	4		T284	12
auto[0]	values[6]	values[3]	233	1			T61	18		T172	7		T276	8
auto[0]	values[6]	values[4]	282	1			T9	6		T73	6		T66	5
auto[0]	values[6]	values[5]	355	1			T291	8		T55	25		T68	16
auto[0]	values[6]	values[6]	546	1			T134	8		T104	12		T213	21
auto[0]	values[6]	values[7]	178	1			T120	10		T253	12		T328	6
auto[0]	values[7]	values[0]	261	1			T207	14		T53	15		T124	10
auto[0]	values[7]	values[1]	346	1			T57	76		T254	61		T199	17
auto[0]	values[7]	values[2]	155	1			T220	2		T267	9		T289	8
auto[0]	values[7]	values[3]	228	1			T278	24		T329	8		T254	17
auto[0]	values[7]	values[4]	212	1			T78	8		T118	12		T303	4
auto[0]	values[7]	values[5]	490	1			T52	20		T211	7		T244	11
auto[0]	values[7]	values[6]	676	1			T255	20		T68	15		T210	70
auto[0]	values[7]	values[7]	322	1			T67	10		T246	6		T280	21
auto[1]	values[0]	values[0]	122	1			T171	6		T69	19		T201	8
auto[1]	values[0]	values[1]	434	1			T58	12		T49	8		T68	11
auto[1]	values[0]	values[2]	257	1			T209	4		T289	9		T247	11
auto[1]	values[0]	values[3]	212	1			T210	37		T330	10		T305	41
auto[1]	values[0]	values[4]	152	1			T261	20		T68	6		T199	8
auto[1]	values[0]	values[5]	178	1			T171	10		T209	10		T201	10
auto[1]	values[0]	values[6]	259	1			T331	6		T171	10		T210	88
auto[1]	values[0]	values[7]	122	1			T332	12		T333	6		T262	64
auto[1]	values[1]	values[0]	186	1			T238	8		T247	11		T243	8
auto[1]	values[1]	values[1]	182	1			T64	6		T69	23		T201	9
auto[1]	values[1]	values[2]	230	1			T59	24		T65	10		T66	4
auto[1]	values[1]	values[3]	169	1			T171	8		T69	10		T210	7
auto[1]	values[1]	values[4]	389	1			T211	91		T69	8		T334	12
auto[1]	values[1]	values[5]	199	1			T251	57		T199	9		T201	5
auto[1]	values[1]	values[6]	88	1			T211	6		T267	7		T201	7
auto[1]	values[1]	values[7]	185	1			T209	23		T199	6		T191	10
auto[1]	values[2]	values[0]	285	1			T55	10		T68	5		T210	8
auto[1]	values[2]	values[1]	137	1			T66	4		T68	1		T210	11
auto[1]	values[2]	values[2]	120	1			T71	20		T210	8		T335	8
auto[1]	values[2]	values[3]	128	1			T251	27		T267	6		T336	12
auto[1]	values[2]	values[4]	235	1			T66	62		T191	11		T337	14
auto[1]	values[2]	values[5]	174	1			T172	13		T312	8		T247	7
auto[1]	values[2]	values[6]	272	1			T61	8		T338	10		T260	14
auto[1]	values[2]	values[7]	183	1			T61	9		T289	13		T245	8
auto[1]	values[3]	values[0]	144	1			T10	8		T254	8		T238	9
auto[1]	values[3]	values[1]	156	1			T339	22		T68	12		T91	8
auto[1]	values[3]	values[2]	275	1			T209	11		T172	14		T297	9
auto[1]	values[3]	values[3]	168	1			T199	7		T272	14		T265	4
auto[1]	values[3]	values[4]	367	1			T66	12		T69	7		T209	11
auto[1]	values[3]	values[5]	217	1			T340	24		T210	8		T172	8
auto[1]	values[3]	values[6]	109	1			T244	8		T254	8		T238	11
auto[1]	values[3]	values[7]	272	1			T55	10		T66	84		T274	10
auto[1]	values[4]	values[0]	70	1			T254	5		T201	9		T258	1
auto[1]	values[4]	values[1]	177	1			T67	8		T172	13		T201	12
auto[1]	values[4]	values[2]	150	1			T211	13		T69	28		T199	9
auto[1]	values[4]	values[3]	251	1			T66	11		T254	11		T274	17
auto[1]	values[4]	values[4]	528	1			T61	11		T66	20		T209	155
auto[1]	values[4]	values[5]	317	1			T242	16		T66	7		T68	10
auto[1]	values[4]	values[6]	85	1			T170	7		T66	4		T209	14
auto[1]	values[4]	values[7]	329	1			T64	10		T248	6		T209	3
auto[1]	values[5]	values[0]	199	1			T56	14		T209	10		T251	11
auto[1]	values[5]	values[1]	265	1			T66	29		T68	5		T69	6
auto[1]	values[5]	values[2]	226	1			T222	20		T210	6		T273	8
auto[1]	values[5]	values[3]	277	1			T171	13		T67	8		T69	9
auto[1]	values[5]	values[4]	279	1			T288	6		T269	28		T305	73
auto[1]	values[5]	values[5]	299	1			T60	22		T267	6		T294	8
auto[1]	values[5]	values[6]	211	1			T66	4		T209	8		T245	5
auto[1]	values[5]	values[7]	138	1			T90	23		T332	10		T194	31
auto[1]	values[6]	values[0]	128	1			T68	8		T254	6		T312	11
auto[1]	values[6]	values[1]	105	1			T299	14		T288	9		T258	14
auto[1]	values[6]	values[2]	193	1			T244	6		T251	9		T312	10
auto[1]	values[6]	values[3]	303	1			T61	26		T172	13		T341	10
auto[1]	values[6]	values[4]	223	1			T66	81		T213	4		T172	26
auto[1]	values[6]	values[5]	264	1			T55	9		T68	4		T251	9
auto[1]	values[6]	values[6]	311	1			T104	8		T213	4		T254	6
auto[1]	values[6]	values[7]	120	1			T289	6		T342	5		T343	6
auto[1]	values[7]	values[0]	307	1			T53	76		T49	6		T211	34
auto[1]	values[7]	values[1]	169	1			T254	10		T199	3		T247	12
auto[1]	values[7]	values[2]	161	1			T267	11		T289	68		T243	11
auto[1]	values[7]	values[3]	279	1			T254	28		T267	18		T243	27
auto[1]	values[7]	values[4]	115	1			T67	9		T68	3		T267	5
auto[1]	values[7]	values[5]	223	1			T211	13		T244	9		T251	7
auto[1]	values[7]	values[6]	256	1			T68	5		T212	8		T210	7
auto[1]	values[7]	values[7]	151	1			T67	10		T280	9		T39	10