Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	374	1			T1	2		T132	2		T104	1
auto[ReadAddrCrossIntoMailbox]	316	1			T132	2		T104	1		T344	2
auto[ReadAddrCrossOutOfMailbox]	292	1			T132	4		T291	4		T104	2
auto[ReadAddrCrossAllMailbox]	257	1			T291	2		T344	2		T61	1
auto[ReadAddrOutsideMailbox]	3669	1			T3	2		T10	4		T11	6

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2384

1

T1

1

T3

1

T10

2

auto[1]

2524

1

T1

1

T3

1

T10

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	791	1			T3	2		T132	4		T58	2
read_ops[0x0b]	814	1			T1	2		T10	2		T11	2
read_ops[0x3b]	860	1			T10	2		T11	2		T132	6
read_ops[0x6b]	841	1			T51	2		T207	2		T52	2
read_ops[0xbb]	795	1			T12	2		T50	2		T217	4
read_ops[0xeb]	807	1			T11	2		T59	2		T291	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	23	1			T300	2		T68	1		T69	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T49	1		T248	1		T300	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T132	1		T61	1		T218	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	34	1			T132	1		T66	1		T218	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	11	1			T291	1		T66	1		T68	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	32	1			T291	1		T66	1		T211	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T61	1		T218	1		T213	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T49	1		T218	1		T210	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	295	1			T3	1		T132	1		T58	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	308	1			T3	1		T132	1		T58	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T1	1		T66	1		T314	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T1	1		T49	2		T314	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T344	1		T66	1		T289	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	37	1			T344	1		T210	2		T251	4
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	17	1			T209	1		T274	1		T345	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T68	1		T69	1		T345	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T344	1		T68	1		T254	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T344	1		T254	1		T345	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	303	1			T10	1		T11	1		T51	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	307	1			T10	1		T11	1		T51	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T132	1		T163	2		T218	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T132	1		T163	2		T66	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T68	1		T317	1		T254	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T61	1		T49	1		T66	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T132	2		T104	1		T244	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T132	2		T69	1		T210	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	26	1			T66	1		T218	1		T67	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	28	1			T218	1		T69	3		T285	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	303	1			T10	1		T11	1		T52	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	324	1			T10	1		T11	1		T52	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T104	1		T66	1		T300	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T66	1		T300	1		T314	4
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T211	1		T254	2		T238	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T248	1		T172	1		T251	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	31	1			T167	1		T211	2		T69	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T167	1		T66	1		T69	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T291	1		T311	1		T310	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T291	1		T248	1		T311	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	317	1			T51	1		T207	1		T52	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	315	1			T51	1		T207	1		T52	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T300	1		T211	1		T68	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T61	1		T300	1		T211	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T66	1		T68	2		T267	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T69	1		T274	1		T346	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T66	1		T210	1		T254	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T104	1		T66	1		T68	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T238	1		T297	1		T345	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T66	1		T201	1		T345	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	298	1			T12	1		T50	1		T217	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	291	1			T12	1		T50	1		T217	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	27	1			T69	1		T347	1		T247	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T66	1		T211	1		T209	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T104	1		T209	1		T238	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T68	1		T238	1		T294	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T291	1		T167	1		T238	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T291	1		T61	1		T167	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T67	1		T172	1		T251	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T66	1		T211	1		T68	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	293	1			T11	1		T59	1		T53	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	315	1			T11	1		T59	1		T55	1