Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4074	1			T78	8		T51	10		T58	12
values[1]	3829	1			T1	8		T12	18		T35	12
values[2]	4798	1			T10	8		T11	6		T118	12
values[3]	3782	1			T304	4		T59	24		T71	20
values[4]	3690	1			T3	6		T63	14		T87	6
values[5]	3600	1			T5	2		T9	6		T76	2
values[6]	3634	1			T37	36		T52	20		T170	20
values[7]	4236	1			T50	2		T120	10		T55	23

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4005	1			T241	12		T249	4		T135	4
values[1]	3402	1			T11	6		T37	36		T24	12
values[2]	4455	1			T87	6		T58	12		T52	20
values[3]	3697	1			T304	4		T55	34		T60	22
values[4]	4536	1			T50	2		T35	12		T220	2
values[5]	4065	1			T9	6		T132	10		T207	14
values[6]	3553	1			T1	8		T3	6		T10	8
values[7]	3930	1			T5	2		T12	18		T76	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30867

1

T1

8

T3

6

T5

2

auto[1]

776

1

T53

2

T55

1

T60

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	644	1			T66	20		T255	20		T210	155
auto[0]	values[0]	values[1]	550	1			T53	89		T253	12		T312	19
auto[0]	values[0]	values[2]	442	1			T58	12		T310	2		T209	161
auto[0]	values[0]	values[3]	458	1			T344	4		T167	4		T209	27
auto[0]	values[0]	values[4]	520	1			T340	24		T259	12		T343	20
auto[0]	values[0]	values[5]	341	1			T66	29		T285	20		T251	48
auto[0]	values[0]	values[6]	605	1			T51	10		T55	20		T57	76
auto[0]	values[0]	values[7]	419	1			T78	8		T309	8		T322	10
auto[0]	values[1]	values[0]	456	1			T286	10		T331	6		T66	29
auto[0]	values[1]	values[1]	553	1			T62	32		T61	41		T65	8
auto[0]	values[1]	values[2]	566	1			T54	20		T68	20		T348	4
auto[0]	values[1]	values[3]	428	1			T211	20		T244	18		T292	16
auto[0]	values[1]	values[4]	509	1			T35	12		T104	20		T166	24
auto[0]	values[1]	values[5]	284	1			T315	4		T349	10		T251	19
auto[0]	values[1]	values[6]	224	1			T1	8		T68	17		T69	20
auto[0]	values[1]	values[7]	711	1			T12	18		T66	24		T209	26
auto[0]	values[2]	values[0]	585	1			T299	14		T329	8		T254	54
auto[0]	values[2]	values[1]	326	1			T11	6		T122	18		T350	22
auto[0]	values[2]	values[2]	805	1			T291	8		T303	4		T66	64
auto[0]	values[2]	values[3]	780	1			T55	34		T60	20		T66	80
auto[0]	values[2]	values[4]	424	1			T221	22		T288	41		T351	24
auto[0]	values[2]	values[5]	893	1			T68	19		T328	6		T210	76
auto[0]	values[2]	values[6]	291	1			T10	8		T68	20		T352	12
auto[0]	values[2]	values[7]	592	1			T118	12		T68	18		T254	26
auto[0]	values[3]	values[0]	569	1			T61	20		T338	10		T211	103
auto[0]	values[3]	values[1]	417	1			T71	20		T308	4		T323	14
auto[0]	values[3]	values[2]	590	1			T49	18		T244	20		T172	21
auto[0]	values[3]	values[3]	181	1			T304	4		T209	26		T353	14
auto[0]	values[3]	values[4]	468	1			T218	14		T68	20		T209	19
auto[0]	values[3]	values[5]	510	1			T59	24		T354	8		T95	20
auto[0]	values[3]	values[6]	394	1			T67	20		T209	19		T293	6
auto[0]	values[3]	values[7]	552	1			T208	20		T311	4		T171	20
auto[0]	values[4]	values[0]	345	1			T171	21		T254	73		T294	21
auto[0]	values[4]	values[1]	529	1			T24	12		T172	52		T355	2
auto[0]	values[4]	values[2]	598	1			T87	6		T69	32		T172	20
auto[0]	values[4]	values[3]	412	1			T68	20		T69	111		T172	19
auto[0]	values[4]	values[4]	387	1			T220	2		T124	10		T199	20
auto[0]	values[4]	values[5]	461	1			T134	8		T73	6		T222	20
auto[0]	values[4]	values[6]	410	1			T3	6		T63	14		T56	14
auto[0]	values[4]	values[7]	450	1			T163	12		T275	14		T212	4
auto[0]	values[5]	values[0]	456	1			T241	12		T249	4		T135	4
auto[0]	values[5]	values[1]	265	1			T266	22		T318	10		T294	20
auto[0]	values[5]	values[2]	411	1			T61	20		T339	22		T211	18
auto[0]	values[5]	values[3]	248	1			T61	40		T261	20		T238	20
auto[0]	values[5]	values[4]	626	1			T66	54		T67	19		T69	28
auto[0]	values[5]	values[5]	692	1			T9	6		T132	10		T207	14
auto[0]	values[5]	values[6]	410	1			T119	6		T282	47		T210	20
auto[0]	values[5]	values[7]	411	1			T5	2		T76	2		T66	85
auto[0]	values[6]	values[0]	426	1			T238	20		T251	70		T356	12
auto[0]	values[6]	values[1]	377	1			T37	36		T320	4		T210	20
auto[0]	values[6]	values[2]	597	1			T52	20		T210	40		T254	34
auto[0]	values[6]	values[3]	464	1			T66	62		T357	2		T243	25
auto[0]	values[6]	values[4]	601	1			T171	16		T67	18		T69	20
auto[0]	values[6]	values[5]	314	1			T248	20		T69	40		T243	20
auto[0]	values[6]	values[6]	443	1			T170	19		T69	19		T209	20
auto[0]	values[6]	values[7]	297	1			T319	6		T305	42		T258	28
auto[0]	values[7]	values[0]	440	1			T171	20		T211	47		T69	18
auto[0]	values[7]	values[1]	291	1			T327	4		T244	19		T288	20
auto[0]	values[7]	values[2]	325	1			T302	16		T211	20		T67	18
auto[0]	values[7]	values[3]	631	1			T64	19		T307	16		T268	76
auto[0]	values[7]	values[4]	885	1			T50	2		T120	10		T55	22
auto[0]	values[7]	values[5]	484	1			T219	6		T172	28		T269	20
auto[0]	values[7]	values[6]	697	1			T256	8		T68	20		T69	26
auto[0]	values[7]	values[7]	397	1			T70	2		T242	16		T284	12
auto[1]	values[0]	values[0]	12	1			T172	1		T265	1		T358	2
auto[1]	values[0]	values[1]	18	1			T53	2		T312	1		T199	1
auto[1]	values[0]	values[2]	11	1			T210	2		T247	2		T359	2
auto[1]	values[0]	values[3]	10	1			T209	1		T360	1		T361	1
auto[1]	values[0]	values[4]	10	1			T343	1		T362	2		T363	4
auto[1]	values[0]	values[5]	7	1			T247	3		T364	2		T365	2
auto[1]	values[0]	values[6]	9	1			T343	1		T366	1		T363	1
auto[1]	values[0]	values[7]	18	1			T251	1		T199	1		T247	2
auto[1]	values[1]	values[0]	7	1			T213	2		T283	1		T363	1
auto[1]	values[1]	values[1]	14	1			T61	1		T65	2		T267	1
auto[1]	values[1]	values[2]	12	1			T199	1		T289	2		T358	2
auto[1]	values[1]	values[3]	18	1			T244	2		T335	2		T199	1
auto[1]	values[1]	values[4]	14	1			T66	1		T213	5		T243	2
auto[1]	values[1]	values[5]	14	1			T251	1		T346	1		T367	8
auto[1]	values[1]	values[6]	9	1			T68	3		T337	1		T368	2
auto[1]	values[1]	values[7]	10	1			T209	2		T172	2		T369	1
auto[1]	values[2]	values[0]	6	1			T254	3		T332	1		T370	2
auto[1]	values[2]	values[1]	4	1			T371	1		T262	1		T372	2
auto[1]	values[2]	values[2]	25	1			T66	2		T199	4		T201	2
auto[1]	values[2]	values[3]	14	1			T60	2		T66	1		T297	1
auto[1]	values[2]	values[4]	15	1			T288	4		T373	2		T39	3
auto[1]	values[2]	values[5]	20	1			T68	1		T210	1		T247	1
auto[1]	values[2]	values[6]	3	1			T374	1		T375	1		T376	1
auto[1]	values[2]	values[7]	15	1			T68	2		T289	2		T91	1
auto[1]	values[3]	values[0]	8	1			T191	4		T377	2		T378	1
auto[1]	values[3]	values[1]	13	1			T49	1		T289	4		T371	1
auto[1]	values[3]	values[2]	23	1			T49	2		T172	1		T174	3
auto[1]	values[3]	values[3]	3	1			T333	1		T379	2		-	-
auto[1]	values[3]	values[4]	11	1			T209	1		T258	1		T373	2
auto[1]	values[3]	values[5]	15	1			T39	2		T272	1		T375	2
auto[1]	values[3]	values[6]	9	1			T209	1		T247	1		T360	4
auto[1]	values[3]	values[7]	19	1			T68	1		T172	1		T267	1
auto[1]	values[4]	values[0]	8	1			T171	2		T254	2		T380	2
auto[1]	values[4]	values[1]	27	1			T95	4		T381	8		T337	1
auto[1]	values[4]	values[2]	12	1			T69	2		T267	1		T269	2
auto[1]	values[4]	values[3]	10	1			T69	4		T172	1		T274	1
auto[1]	values[4]	values[4]	8	1			T265	1		T369	2		T193	1
auto[1]	values[4]	values[5]	13	1			T209	3		T288	1		T238	2
auto[1]	values[4]	values[6]	8	1			T66	1		T172	1		T265	1
auto[1]	values[4]	values[7]	12	1			T212	4		T305	1		T95	1
auto[1]	values[5]	values[0]	15	1			T171	1		T297	3		T174	3
auto[1]	values[5]	values[1]	4	1			T40	1		T194	1		T382	2
auto[1]	values[5]	values[2]	16	1			T211	2		T383	4		T366	3
auto[1]	values[5]	values[3]	6	1			T61	4		T384	1		T378	1
auto[1]	values[5]	values[4]	13	1			T66	3		T67	1		T69	2
auto[1]	values[5]	values[5]	2	1			T95	1		T385	1		-	-
auto[1]	values[5]	values[6]	11	1			T342	1		T362	3		T262	2
auto[1]	values[5]	values[7]	14	1			T66	1		T201	4		T294	1
auto[1]	values[6]	values[0]	16	1			T95	2		T91	2		T336	4
auto[1]	values[6]	values[1]	10	1			T346	2		T306	4		T386	1
auto[1]	values[6]	values[2]	15	1			T210	3		T272	2		T333	3
auto[1]	values[6]	values[3]	17	1			T66	1		T243	2		T305	3
auto[1]	values[6]	values[4]	26	1			T171	4		T67	2		T69	2
auto[1]	values[6]	values[5]	12	1			T69	1		T294	3		T191	2
auto[1]	values[6]	values[6]	14	1			T170	1		T69	2		T201	1
auto[1]	values[6]	values[7]	5	1			T258	1		T359	1		T262	1
auto[1]	values[7]	values[0]	12	1			T211	2		T69	2		T258	3
auto[1]	values[7]	values[1]	4	1			T244	1		T387	3		-	-
auto[1]	values[7]	values[2]	7	1			T67	2		T269	2		T178	1
auto[1]	values[7]	values[3]	17	1			T64	1		T201	1		T258	1
auto[1]	values[7]	values[4]	19	1			T55	1		T64	1		T254	2
auto[1]	values[7]	values[5]	3	1			T373	1		T342	1		T375	1
auto[1]	values[7]	values[6]	16	1			T69	1		T247	2		T243	2
auto[1]	values[7]	values[7]	8	1			T312	2		T267	1		T199	1