Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	797	1			T15	31		T84	27		T33	18
all_values[1]	797	1			T15	31		T84	27		T33	18
all_values[2]	797	1			T15	31		T84	27		T33	18
all_values[3]	797	1			T15	31		T84	27		T33	18
all_values[4]	797	1			T15	31		T84	27		T33	18
all_values[5]	797	1			T15	31		T84	27		T33	18
all_values[6]	797	1			T15	31		T84	27		T33	18
all_values[7]	797	1			T15	31		T84	27		T33	18

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3421

1

T15

124

T84

116

T33

62

auto[1]

2955

1

T15

124

T84

100

T33

82

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2465

1

T15

95

T84

83

T33

48

auto[1]

3911

1

T15

153

T84

133

T33

96

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3600

1

T15

138

T84

123

T33

75

auto[1]

2776

1

T15

110

T84

93

T33

69

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	159	1			T15	10		T84	8		T205	6
all_values[0]	auto[0]	auto[0]	auto[1]	82	1			T15	1		T84	3		T33	2
all_values[0]	auto[0]	auto[1]	auto[0]	117	1			T15	4		T84	1		T33	4
all_values[0]	auto[0]	auto[1]	auto[1]	92	1			T15	2		T84	4		T33	1
all_values[0]	auto[1]	auto[0]	auto[1]	183	1			T15	5		T84	7		T33	4
all_values[0]	auto[1]	auto[1]	auto[1]	164	1			T15	9		T84	4		T33	7
all_values[1]	auto[0]	auto[0]	auto[0]	165	1			T15	3		T84	6		T33	6
all_values[1]	auto[0]	auto[0]	auto[1]	68	1			T15	1		T84	3		T33	1
all_values[1]	auto[0]	auto[1]	auto[0]	130	1			T15	6		T84	2		T33	4
all_values[1]	auto[0]	auto[1]	auto[1]	89	1			T15	7		T84	4		T206	1
all_values[1]	auto[1]	auto[0]	auto[1]	195	1			T15	5		T84	6		T33	4
all_values[1]	auto[1]	auto[1]	auto[1]	150	1			T15	9		T84	6		T33	3
all_values[2]	auto[0]	auto[0]	auto[0]	161	1			T15	7		T84	2		T33	2
all_values[2]	auto[0]	auto[0]	auto[1]	97	1			T15	4		T84	5		T33	2
all_values[2]	auto[0]	auto[1]	auto[0]	129	1			T15	5		T84	6		T33	5
all_values[2]	auto[0]	auto[1]	auto[1]	68	1			T15	2		T84	2		T33	1
all_values[2]	auto[1]	auto[0]	auto[1]	192	1			T15	5		T84	5		T33	5
all_values[2]	auto[1]	auto[1]	auto[1]	150	1			T15	8		T84	7		T33	3
all_values[3]	auto[0]	auto[0]	auto[0]	156	1			T84	9		T33	2		T206	3
all_values[3]	auto[0]	auto[0]	auto[1]	88	1			T15	7		T84	2		T33	1
all_values[3]	auto[0]	auto[1]	auto[0]	128	1			T15	9		T84	5		T33	2
all_values[3]	auto[0]	auto[1]	auto[1]	84	1			T15	6		T84	1		T33	2
all_values[3]	auto[1]	auto[0]	auto[1]	181	1			T15	5		T84	3		T33	5
all_values[3]	auto[1]	auto[1]	auto[1]	160	1			T15	4		T84	7		T33	6
all_values[4]	auto[0]	auto[0]	auto[0]	159	1			T15	11		T84	4		T33	2
all_values[4]	auto[0]	auto[0]	auto[1]	71	1			T15	1		T84	3		T33	3
all_values[4]	auto[0]	auto[1]	auto[0]	132	1			T15	7		T84	2		T33	5
all_values[4]	auto[0]	auto[1]	auto[1]	80	1			T15	1		T84	3		T33	2
all_values[4]	auto[1]	auto[0]	auto[1]	193	1			T15	8		T84	6		T33	3
all_values[4]	auto[1]	auto[1]	auto[1]	162	1			T15	3		T84	9		T33	3
all_values[5]	auto[0]	auto[0]	auto[0]	216	1			T15	8		T84	13		T33	2
all_values[5]	auto[0]	auto[1]	auto[0]	220	1			T15	9		T84	7		T33	6
all_values[5]	auto[1]	auto[0]	auto[1]	194	1			T15	10		T84	4		T33	3
all_values[5]	auto[1]	auto[1]	auto[1]	167	1			T15	4		T84	3		T33	7
all_values[6]	auto[0]	auto[0]	auto[0]	159	1			T15	4		T84	5		T33	3
all_values[6]	auto[0]	auto[0]	auto[1]	74	1			T15	2		T84	3		T33	1
all_values[6]	auto[0]	auto[1]	auto[0]	126	1			T15	4		T84	2		T33	3
all_values[6]	auto[0]	auto[1]	auto[1]	82	1			T15	3		T84	2		T33	3
all_values[6]	auto[1]	auto[0]	auto[1]	196	1			T15	13		T84	4		T33	3
all_values[6]	auto[1]	auto[1]	auto[1]	160	1			T15	5		T84	11		T33	5
all_values[7]	auto[0]	auto[0]	auto[0]	164	1			T15	3		T84	5		T33	2
all_values[7]	auto[0]	auto[0]	auto[1]	81	1			T15	3		T84	3		T33	1
all_values[7]	auto[0]	auto[1]	auto[0]	144	1			T15	5		T84	6		T205	4
all_values[7]	auto[0]	auto[1]	auto[1]	79	1			T15	3		T84	2		T33	7
all_values[7]	auto[1]	auto[0]	auto[1]	187	1			T15	8		T84	7		T33	5
all_values[7]	auto[1]	auto[1]	auto[1]	142	1			T15	9		T84	4		T33	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal