Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1705

1

T6

5

T26

6

T28

3

auto[1]

1613

1

T4

1

T6

2

T26

6

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1805

1

T4

1

T6

7

T28

4

auto[1]

1513

1

T26

12

T28

2

T29

46

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2611

1

T6

5

T26

12

T28

5

auto[1]

707

1

T4

1

T6

2

T28

1

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	654	1			T6	1		T26	2		T28	2
valid[1]	625	1			T4	1		T6	2		T26	3
valid[2]	645	1			T6	2		T26	3		T28	1
valid[3]	703	1			T6	1		T26	2		T28	2
valid[4]	691	1			T6	1		T26	2		T28	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	124	1			T6	1		T43	1		T406	1
auto[0]	auto[0]	valid[0]	auto[1]	148	1			T26	2		T29	1		T30	1
auto[0]	auto[0]	valid[1]	auto[0]	95	1			T6	1		T55	1		T48	1
auto[0]	auto[0]	valid[1]	auto[1]	147	1			T26	1		T29	7		T89	1
auto[0]	auto[0]	valid[2]	auto[0]	92	1			T6	1		T405	1		T403	1
auto[0]	auto[0]	valid[2]	auto[1]	164	1			T26	1		T29	7		T32	1
auto[0]	auto[0]	valid[3]	auto[0]	111	1			T28	1		T43	2		T405	1
auto[0]	auto[0]	valid[3]	auto[1]	182	1			T28	1		T29	1		T30	1
auto[0]	auto[0]	valid[4]	auto[0]	128	1			T6	1		T41	1		T42	1
auto[0]	auto[0]	valid[4]	auto[1]	159	1			T26	2		T29	6		T89	3
auto[0]	auto[1]	valid[0]	auto[0]	95	1			T403	2		T48	2		T396	1
auto[0]	auto[1]	valid[0]	auto[1]	141	1			T28	1		T29	8		T32	1
auto[0]	auto[1]	valid[1]	auto[0]	111	1			T6	1		T43	2		T55	1
auto[0]	auto[1]	valid[1]	auto[1]	126	1			T26	2		T29	2		T89	4
auto[0]	auto[1]	valid[2]	auto[0]	101	1			T28	1		T41	1		T43	1
auto[0]	auto[1]	valid[2]	auto[1]	149	1			T26	2		T29	5		T30	1
auto[0]	auto[1]	valid[3]	auto[0]	118	1			T55	1		T403	1		T404	1
auto[0]	auto[1]	valid[3]	auto[1]	148	1			T26	2		T29	3		T89	7
auto[0]	auto[1]	valid[4]	auto[0]	123	1			T28	1		T43	1		T404	1
auto[0]	auto[1]	valid[4]	auto[1]	149	1			T29	6		T30	2		T89	5
auto[1]	auto[0]	valid[0]	auto[0]	65	1			T28	1		T396	1		T38	2
auto[1]	auto[0]	valid[1]	auto[0]	79	1			T31	1		T48	2		T137	1
auto[1]	auto[0]	valid[2]	auto[0]	64	1			T6	1		T43	1		T403	1
auto[1]	auto[0]	valid[3]	auto[0]	83	1			T43	2		T55	1		T405	1
auto[1]	auto[0]	valid[4]	auto[0]	64	1			T403	1		T404	1		T48	1
auto[1]	auto[1]	valid[0]	auto[0]	81	1			T48	2		T164	1		T257	3
auto[1]	auto[1]	valid[1]	auto[0]	67	1			T4	1		T216	2		T257	1
auto[1]	auto[1]	valid[2]	auto[0]	75	1			T403	1		T404	1		T48	2
auto[1]	auto[1]	valid[3]	auto[0]	61	1			T6	1		T403	1		T48	1
auto[1]	auto[1]	valid[4]	auto[0]	68	1			T43	1		T405	1		T404	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal