Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46755

1

T4

28

T6

191

T27

5

auto[1]

15188

1

T4

4

T26

12

T28

10

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44946

1

T4

20

T6

135

T26

12

auto[1]

16997

1

T4

12

T6

56

T27

1

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	31915	1			T4	15		T6	97		T26	12
others[1]	5247	1			T4	3		T6	14		T28	10
others[2]	5305	1			T6	20		T27	1		T28	7
others[3]	5837	1			T4	6		T6	19		T28	6
interest[1]	3392	1			T4	1		T6	7		T28	4
interest[4]	20969	1			T4	13		T6	67		T26	12
interest[64]	10247	1			T4	7		T6	34		T28	11

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15287	1			T4	10		T6	66		T27	3
auto[0]	auto[0]	others[1]	2512	1			T4	1		T6	10		T28	7
auto[0]	auto[0]	others[2]	2577	1			T6	15		T27	1		T28	2
auto[0]	auto[0]	others[3]	2815	1			T4	2		T6	15		T28	5
auto[0]	auto[0]	interest[1]	1641	1			T4	1		T6	5		T28	3
auto[0]	auto[0]	interest[4]	10033	1			T4	8		T6	47		T27	1
auto[0]	auto[0]	interest[64]	4926	1			T4	2		T6	24		T28	5
auto[0]	auto[1]	others[0]	7889	1			T4	1		T26	12		T28	6
auto[0]	auto[1]	others[1]	1289	1			T29	38		T32	4		T89	36
auto[0]	auto[1]	others[2]	1310	1			T28	1		T29	47		T32	1
auto[0]	auto[1]	others[3]	1387	1			T4	1		T29	43		T32	5
auto[0]	auto[1]	interest[1]	842	1			T28	1		T29	31		T32	1
auto[0]	auto[1]	interest[4]	5249	1			T4	1		T26	12		T28	3
auto[0]	auto[1]	interest[64]	2471	1			T4	2		T28	2		T29	73
auto[1]	auto[0]	others[0]	8739	1			T4	4		T6	31		T27	1
auto[1]	auto[0]	others[1]	1446	1			T4	2		T6	4		T28	3
auto[1]	auto[0]	others[2]	1418	1			T6	5		T28	4		T23	1
auto[1]	auto[0]	others[3]	1635	1			T4	3		T6	4		T28	1
auto[1]	auto[0]	interest[1]	909	1			T6	2		T23	1		T44	1
auto[1]	auto[0]	interest[4]	5687	1			T4	4		T6	20		T28	5
auto[1]	auto[0]	interest[64]	2850	1			T4	3		T6	10		T28	4

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal