Unified Coverage Report :: Cond split page

Go back

 LINE       20341
 EXPRESSION (addr_hit[34] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T81,T127,T128
1	1	1	Covered	T1,T3,T5

 LINE       20368
 EXPRESSION (addr_hit[35] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T81,T127,T138
1	1	1	Covered	T1,T3,T5

 LINE       20395
 EXPRESSION (addr_hit[36] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T81,T127,T128
1	1	1	Covered	T1,T3,T5

 LINE       20422
 EXPRESSION (addr_hit[37] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T81,T127,T141
1	1	1	Covered	T1,T3,T5

 LINE       20449
 EXPRESSION (addr_hit[38] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T127,T141,T140
1	1	1	Covered	T1,T3,T5

 LINE       20476
 EXPRESSION (addr_hit[39] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T127,T128,T141
1	1	1	Covered	T1,T3,T5

 LINE       20503
 EXPRESSION (addr_hit[40] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T127,T139,T140
1	1	1	Covered	T1,T3,T5

 LINE       20530
 EXPRESSION (addr_hit[41] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T138,T140,T144
1	1	1	Covered	T1,T3,T5

 LINE       20557
 EXPRESSION (addr_hit[42] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T81,T141,T140
1	1	1	Covered	T1,T3,T5

 LINE       20584
 EXPRESSION (addr_hit[43] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T127,T141,T139
1	1	1	Covered	T1,T3,T5

 LINE       20611
 EXPRESSION (addr_hit[44] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T81,T139,T140
1	1	1	Covered	T1,T3,T5

 LINE       20638
 EXPRESSION (addr_hit[45] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T127,T128,T138
1	1	1	Covered	T1,T3,T5

 LINE       20665
 EXPRESSION (addr_hit[46] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T127,T128,T145
1	1	1	Covered	T1,T3,T5

 LINE       20692
 EXPRESSION (addr_hit[47] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T141,T140,T144
1	1	1	Covered	T1,T3,T5

 LINE       20719
 EXPRESSION (addr_hit[48] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T81,T127,T128
1	1	1	Covered	T1,T3,T5

 LINE       20746
 EXPRESSION (addr_hit[49] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T127,T129,T138
1	1	1	Covered	T1,T3,T5

 LINE       20773
 EXPRESSION (addr_hit[50] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T81,T127,T128
1	1	1	Covered	T1,T3,T5

 LINE       20800
 EXPRESSION (addr_hit[51] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T81,T127,T128
1	1	1	Covered	T1,T3,T5

 LINE       20827
 EXPRESSION (addr_hit[52] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T81,T128,T129
1	1	1	Covered	T1,T3,T5

 LINE       20854
 EXPRESSION (addr_hit[53] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T81,T138,T139
1	1	1	Covered	T1,T3,T5

 LINE       20881
 EXPRESSION (addr_hit[54] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T127,T138,T139
1	1	1	Covered	T1,T3,T5

 LINE       20908
 EXPRESSION (addr_hit[55] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T5,T7
1	1	0	Covered	T128,T129,T140
1	1	1	Covered	T3,T5,T7

 LINE       20913
 EXPRESSION (addr_hit[56] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T5,T7
1	1	0	Covered	T81,T127,T141
1	1	1	Covered	T3,T5,T7

 LINE       20918
 EXPRESSION (addr_hit[57] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T5,T7,T9
1	1	0	Covered	T127,T128,T138
1	1	1	Covered	T5,T7,T9

 LINE       20923
 EXPRESSION (addr_hit[58] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T5,T7,T9
1	1	0	Covered	T127,T128,T129
1	1	1	Covered	T5,T7,T9

 LINE       20928
 EXPRESSION (addr_hit[60] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T82,T128,T129
1	1	1	Covered	T4,T6,T26

 LINE       20939
 EXPRESSION (addr_hit[61] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T6,T27
1	1	0	Not Covered
1	1	1	Covered	T4,T6,T28

 LINE       20940
 EXPRESSION (addr_hit[61] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T4,T6,T27
1	1	0	Covered	T127,T141,T140
1	1	1	Covered	T4,T6,T27

 LINE       20943
 EXPRESSION (addr_hit[62] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T4,T6,T10
1	1	0	Covered	T127,T128,T138
1	1	1	Covered	T4,T6,T26

 LINE       20952
 EXPRESSION (addr_hit[63] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T81,T128,T138
1	1	1	Covered	T4,T6,T26

 LINE       20955
 EXPRESSION (addr_hit[64] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T4,T6,T10
1	1	0	Covered	T81,T127,T128
1	1	1	Covered	T4,T6,T26

 LINE       20958
 EXPRESSION (addr_hit[65] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T4,T6,T10
1	1	0	Covered	T81,T127,T141
1	1	1	Covered	T4,T6,T28

 LINE       20961
 EXPRESSION (addr_hit[66] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T4,T6,T28
1	1	0	Covered	T127,T146,T144
1	1	1	Covered	T4,T6,T28

 LINE       20964
 EXPRESSION (addr_hit[67] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T4,T6,T28
1	1	0	Covered	T127,T128,T141
1	1	1	Covered	T4,T6,T28

 LINE       20967
 EXPRESSION (addr_hit[68] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T4,T6,T10
1	1	0	Covered	T81,T127,T141
1	1	1	Covered	T4,T6,T28

 LINE       20970
 EXPRESSION (addr_hit[69] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T4,T6,T28
1	1	0	Covered	T127,T138,T141
1	1	1	Covered	T4,T6,T28

 LINE       20975
 EXPRESSION (addr_hit[70] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T81,T127,T128
1	1	1	Covered	T4,T6,T28

 LINE       20978
 EXPRESSION (addr_hit[71] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T4,T6,T27

 LINE       20979
 EXPRESSION (addr_hit[72] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T128,T140,T143
1	1	1	Covered	T4,T6,T27