Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2651320	1			T1	1		T2	1		T3	1
all_values[1]	2651320	1			T1	1		T2	1		T3	1
all_values[2]	2651320	1			T1	1		T2	1		T3	1
all_values[3]	2651320	1			T1	1		T2	1		T3	1
all_values[4]	2651320	1			T1	1		T2	1		T3	1
all_values[5]	2651320	1			T1	1		T2	1		T3	1
all_values[6]	2651320	1			T1	1		T2	1		T3	1
all_values[7]	2651320	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20930977

1

T1

8

T2

8

T3

8

auto[1]

279583

1

T21

90

T34

18

T35

11758

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21184571

1

T1

8

T2

8

T3

8

auto[1]

25989

1

T52

1

T47

248

T49

113

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2623256	1			T1	1		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	12278	1			T47	93		T49	75		T45	19
all_values[0]	auto[1]	auto[0]	15499	1			T21	8		T34	1		T35	10
all_values[0]	auto[1]	auto[1]	287	1			T21	7		T35	2		T36	1
all_values[1]	auto[0]	auto[0]	2591617	1			T1	1		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	7893	1			T47	91		T49	19		T21	19
all_values[1]	auto[1]	auto[0]	51404	1			T21	8		T34	5		T35	2926
all_values[1]	auto[1]	auto[1]	406	1			T21	12		T35	4		T36	1
all_values[2]	auto[0]	auto[0]	2613346	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	2911	1			T47	64		T49	19		T21	23
all_values[2]	auto[1]	auto[0]	34736	1			T21	4		T34	1		T35	6
all_values[2]	auto[1]	auto[1]	327	1			T21	3		T35	5		T36	4
all_values[3]	auto[0]	auto[0]	2625540	1			T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	209	1			T52	1		T21	7		T34	4
all_values[3]	auto[1]	auto[0]	25378	1			T21	2		T35	2923		T172	5
all_values[3]	auto[1]	auto[1]	193	1			T21	6		T35	3		T36	4
all_values[4]	auto[0]	auto[0]	2593700	1			T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	183	1			T21	4		T35	4		T36	1
all_values[4]	auto[1]	auto[0]	57243	1			T21	5		T34	5		T35	6
all_values[4]	auto[1]	auto[1]	194	1			T21	5		T35	2		T36	6
all_values[5]	auto[0]	auto[0]	2623086	1			T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	174	1			T21	3		T34	2		T35	3
all_values[5]	auto[1]	auto[0]	27875	1			T21	11		T34	4		T35	4
all_values[5]	auto[1]	auto[1]	185	1			T21	2		T35	4		T36	3
all_values[6]	auto[0]	auto[0]	2646339	1			T1	1		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	192	1			T21	6		T35	7		T36	3
all_values[6]	auto[1]	auto[0]	4604	1			T21	3		T34	1		T35	2926
all_values[6]	auto[1]	auto[1]	185	1			T21	7		T35	2		T36	6
all_values[7]	auto[0]	auto[0]	2590073	1			T1	1		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	180	1			T21	10		T35	3		T36	2
all_values[7]	auto[1]	auto[0]	60875	1			T21	5		T34	1		T35	2931
all_values[7]	auto[1]	auto[1]	192	1			T21	2		T35	4		T36	1