Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 93.99 98.62 89.36 97.19 95.45 99.26


Total tests in report: 1131
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
63.04 63.04 92.50 92.50 78.41 78.41 62.99 62.99 35.56 35.56 88.96 88.96 71.69 71.69 11.14 11.14 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.265983733
77.25 14.22 96.20 3.70 86.30 7.88 65.35 2.36 84.44 48.89 94.08 5.12 81.37 9.67 33.02 21.88 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.3261862406
83.83 6.58 97.16 0.96 89.83 3.53 87.99 22.64 88.89 4.44 95.45 1.37 84.50 3.13 43.02 10.00 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_all.860013610
86.95 3.12 97.67 0.51 91.37 1.54 90.35 2.36 91.11 2.22 96.06 0.61 84.92 0.43 57.18 14.16 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_stress_all.3387491874
88.81 1.86 97.75 0.08 91.52 0.15 90.35 0.00 93.33 2.22 96.25 0.19 85.06 0.14 67.43 10.25 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_stress_all.4109894598
90.44 1.63 97.75 0.00 91.69 0.17 91.14 0.79 93.33 0.00 96.26 0.02 93.74 8.68 69.16 1.73 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2377579817
91.41 0.96 98.21 0.46 92.45 0.76 91.93 0.79 93.33 0.00 96.96 0.69 93.74 0.00 73.22 4.06 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_intercept.1703677810
92.12 0.72 98.21 0.00 92.49 0.04 91.93 0.00 93.33 0.00 96.96 0.00 93.88 0.14 78.07 4.85 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.1496063403
92.80 0.68 98.23 0.02 92.49 0.00 96.65 4.72 93.33 0.00 96.96 0.00 93.88 0.00 78.07 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_ram_cfg.1517390170
93.40 0.60 98.23 0.00 92.49 0.00 96.65 0.00 93.33 0.00 96.96 0.00 93.88 0.00 82.28 4.21 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_stress_all.98676996
93.78 0.37 98.23 0.00 92.49 0.00 96.65 0.00 93.33 0.00 96.96 0.00 93.88 0.00 84.90 2.62 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_stress_all.1390012560
94.10 0.32 98.23 0.01 92.53 0.04 98.43 1.77 93.33 0.00 96.97 0.02 94.03 0.14 85.15 0.25 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_sec_cm.1267117875
94.39 0.30 98.23 0.00 92.59 0.06 98.43 0.00 93.33 0.00 97.01 0.03 94.03 0.00 87.13 1.98 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.2140952616
94.63 0.24 98.23 0.00 92.59 0.00 98.43 0.00 93.33 0.00 97.01 0.00 94.03 0.00 88.81 1.68 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_stress_all.645404168
94.85 0.21 98.35 0.11 93.00 0.41 98.43 0.00 93.33 0.00 97.16 0.15 94.59 0.57 89.06 0.25 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode.1670987307
95.02 0.18 98.35 0.00 93.00 0.00 98.43 0.00 93.33 0.00 97.16 0.00 94.59 0.00 90.30 1.24 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_stress_all.409825172
95.18 0.16 98.35 0.00 93.00 0.00 98.43 0.00 93.33 0.00 97.16 0.00 94.59 0.00 91.39 1.09 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.951262528
95.33 0.15 98.36 0.01 93.07 0.07 98.43 0.00 93.33 0.00 97.18 0.02 94.59 0.00 92.33 0.94 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.2695573709
95.47 0.14 98.36 0.00 93.83 0.76 98.43 0.00 93.33 0.00 97.19 0.02 94.59 0.00 92.52 0.20 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.3846793171
95.59 0.13 98.36 0.00 93.83 0.00 98.43 0.00 93.33 0.00 97.19 0.00 94.59 0.00 93.42 0.89 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.3334419631
95.72 0.12 98.36 0.00 93.84 0.01 98.43 0.00 93.33 0.00 97.19 0.00 95.45 0.85 93.42 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.431521837
95.82 0.11 98.36 0.00 93.84 0.00 98.43 0.00 93.33 0.00 97.19 0.00 95.45 0.00 94.16 0.74 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.3501520388
95.92 0.10 98.36 0.00 93.86 0.01 98.43 0.00 93.33 0.00 97.19 0.00 95.45 0.00 94.85 0.69 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_all.3615844427
96.00 0.08 98.36 0.00 93.86 0.00 98.43 0.00 93.33 0.00 97.19 0.00 95.45 0.00 95.40 0.54 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_stress_all.2918665311
96.06 0.06 98.36 0.00 93.86 0.00 98.43 0.00 93.33 0.00 97.19 0.00 95.45 0.00 95.79 0.40 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm_min_idle.2130026230
96.11 0.06 98.36 0.00 93.86 0.00 98.43 0.00 93.33 0.00 97.19 0.00 95.45 0.00 96.19 0.40 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_and_tpm_min_idle.1960012084
96.16 0.04 98.36 0.00 93.86 0.00 98.43 0.00 93.33 0.00 97.19 0.00 95.45 0.00 96.49 0.30 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.1496124044
96.20 0.04 98.36 0.00 93.86 0.00 98.43 0.00 93.33 0.00 97.19 0.00 95.45 0.00 96.78 0.30 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_all.2990649995
96.24 0.04 98.38 0.03 93.89 0.04 98.62 0.20 93.33 0.00 97.19 0.00 95.45 0.00 96.78 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_alert_test.2223853726
96.27 0.04 98.38 0.00 93.89 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 97.03 0.25 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm_min_idle.916641616
96.31 0.04 98.38 0.00 93.89 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 97.28 0.25 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_mode_ignore_cmds.1582101536
96.34 0.03 98.38 0.00 93.89 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 97.48 0.20 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode.3097287928
96.36 0.02 98.38 0.00 93.91 0.01 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 97.62 0.15 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.3555346730
96.38 0.02 98.38 0.00 93.91 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 97.77 0.15 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.1679755073
96.40 0.02 98.38 0.00 93.91 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 97.92 0.15 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_stress_all.66897696
96.42 0.02 98.38 0.00 93.91 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.07 0.15 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_mode_ignore_cmds.3080278467
96.44 0.02 98.38 0.00 93.91 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.22 0.15 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_all.38586018
96.46 0.02 98.38 0.00 93.91 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.37 0.15 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_stress_all.4037919230
96.49 0.02 98.38 0.00 93.91 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.51 0.15 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.1406766546
96.50 0.01 98.38 0.00 93.91 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.61 0.10 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_stress_all.195297096
96.51 0.01 98.38 0.00 93.91 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.71 0.10 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm_min_idle.1482028617
96.52 0.01 98.38 0.00 93.97 0.06 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.71 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.4169786968
96.53 0.01 98.38 0.00 93.97 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.76 0.05 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.4159454486
96.54 0.01 98.38 0.00 93.97 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.81 0.05 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.3559535389
96.54 0.01 98.38 0.00 93.97 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.86 0.05 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_mailbox.2604577781
96.55 0.01 98.38 0.00 93.97 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.91 0.05 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode_ignore_cmds.2078018396
96.56 0.01 98.38 0.00 93.97 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 98.96 0.05 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_cfg_cmd.1004488235
96.57 0.01 98.38 0.00 93.97 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.01 0.05 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm_min_idle.224168168
96.57 0.01 98.38 0.00 93.97 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.06 0.05 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_and_tpm.434247032
96.58 0.01 98.38 0.00 93.97 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.11 0.05 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm_min_idle.274606571
96.59 0.01 98.38 0.00 93.97 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.16 0.05 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_mode_ignore_cmds.511821310
96.59 0.01 98.38 0.00 93.97 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.21 0.05 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_mode.3319186080
96.60 0.01 98.38 0.00 93.97 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.26 0.05 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_stress_all.3239608342
96.60 0.01 98.38 0.00 93.98 0.01 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.3190973252
96.60 0.01 98.38 0.00 93.99 0.01 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1570267519

Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.2749140307
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.4282241477
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1785265879
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3285093722
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.914606802
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.3504597745
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.1574910219
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.979467159
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1767554549
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.3065047385
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2347178368
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.4181098131
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2334780960
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.2575136823
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.3965673327
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.331472883
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.3653020749
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1438632428
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.3684844447
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.2342005238
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2298522067
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.1911613463
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.172067631
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.909377061
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.798812312
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1428899768
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.3255759243
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.2943258008
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1344715853
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.598142184
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.7287157
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/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_cfg_cmd.1188681856
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/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.1866990560
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_rw.400664618
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.1204770118
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_upload.3440063639



Total test records in report: 1131
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_csb_read.2296564959 Sep 11 12:27:43 PM UTC 24 Sep 11 12:27:45 PM UTC 24 44532377 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_ram_cfg.1517390170 Sep 11 12:27:46 PM UTC 24 Sep 11 12:27:49 PM UTC 24 15661171 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.1371427281 Sep 11 12:27:48 PM UTC 24 Sep 11 12:27:59 PM UTC 24 1164228209 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.1382442643 Sep 11 12:27:59 PM UTC 24 Sep 11 12:28:01 PM UTC 24 17103710 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_rw.4123764923 Sep 11 12:28:02 PM UTC 24 Sep 11 12:28:05 PM UTC 24 173237350 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.265983733 Sep 11 12:28:06 PM UTC 24 Sep 11 12:28:20 PM UTC 24 447999835 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.27717331 Sep 11 12:28:21 PM UTC 24 Sep 11 12:28:31 PM UTC 24 7120964205 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_intercept.2082455327 Sep 11 12:28:27 PM UTC 24 Sep 11 12:28:33 PM UTC 24 72895797 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_all.860013610 Sep 11 12:27:49 PM UTC 24 Sep 11 12:28:34 PM UTC 24 5393133165 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_cfg_cmd.3198854590 Sep 11 12:28:35 PM UTC 24 Sep 11 12:28:40 PM UTC 24 46775206 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode.1376448196 Sep 11 12:28:41 PM UTC 24 Sep 11 12:28:47 PM UTC 24 126297492 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_upload.1406654776 Sep 11 12:28:34 PM UTC 24 Sep 11 12:28:49 PM UTC 24 3461106194 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.725077693 Sep 11 12:28:50 PM UTC 24 Sep 11 12:29:02 PM UTC 24 2142656631 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_all.3098398596 Sep 11 12:29:03 PM UTC 24 Sep 11 12:29:05 PM UTC 24 73521890 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_sec_cm.1267117875 Sep 11 12:29:43 PM UTC 24 Sep 11 12:29:46 PM UTC 24 350540873 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_alert_test.2223853726 Sep 11 12:29:47 PM UTC 24 Sep 11 12:29:49 PM UTC 24 37590800 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_csb_read.1373381356 Sep 11 12:29:50 PM UTC 24 Sep 11 12:29:53 PM UTC 24 36182131 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_all.4096513815 Sep 11 12:30:06 PM UTC 24 Sep 11 12:30:09 PM UTC 24 58666237 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_mailbox.2604577781 Sep 11 12:28:33 PM UTC 24 Sep 11 12:30:11 PM UTC 24 25326977493 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.2133521277 Sep 11 12:30:09 PM UTC 24 Sep 11 12:30:12 PM UTC 24 61380383 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_rw.3434006689 Sep 11 12:30:11 PM UTC 24 Sep 11 12:30:15 PM UTC 24 158256331 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.653273191 Sep 11 12:30:16 PM UTC 24 Sep 11 12:30:25 PM UTC 24 6919276504 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_intercept.1703677810 Sep 11 12:30:17 PM UTC 24 Sep 11 12:30:30 PM UTC 24 2295045093 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.3604750883 Sep 11 12:30:13 PM UTC 24 Sep 11 12:30:33 PM UTC 24 13877133153 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.1496124044 Sep 11 12:29:56 PM UTC 24 Sep 11 12:30:34 PM UTC 24 6708014599 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode.2617362662 Sep 11 12:30:31 PM UTC 24 Sep 11 12:30:40 PM UTC 24 300203279 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.2328784859 Sep 11 12:30:35 PM UTC 24 Sep 11 12:30:41 PM UTC 24 181209719 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_cfg_cmd.1565130592 Sep 11 12:30:30 PM UTC 24 Sep 11 12:30:45 PM UTC 24 10910562304 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_sec_cm.474744509 Sep 11 12:30:46 PM UTC 24 Sep 11 12:30:49 PM UTC 24 80114093 ps
T85 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_alert_test.982671639 Sep 11 12:30:49 PM UTC 24 Sep 11 12:30:51 PM UTC 24 10734939 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_csb_read.3109298375 Sep 11 12:30:52 PM UTC 24 Sep 11 12:30:55 PM UTC 24 20007933 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.2598096710 Sep 11 12:30:59 PM UTC 24 Sep 11 12:31:04 PM UTC 24 245700970 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.1355904028 Sep 11 12:31:05 PM UTC 24 Sep 11 12:31:07 PM UTC 24 64960894 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_rw.3255153100 Sep 11 12:31:08 PM UTC 24 Sep 11 12:31:11 PM UTC 24 29912655 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.1598986479 Sep 11 12:31:15 PM UTC 24 Sep 11 12:31:20 PM UTC 24 33728595 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_upload.1680257878 Sep 11 12:30:26 PM UTC 24 Sep 11 12:31:25 PM UTC 24 16321221974 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_all.3615844427 Sep 11 12:31:00 PM UTC 24 Sep 11 12:31:28 PM UTC 24 2949507751 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_intercept.36071934 Sep 11 12:31:20 PM UTC 24 Sep 11 12:31:29 PM UTC 24 612940525 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.3089108024 Sep 11 12:31:12 PM UTC 24 Sep 11 12:31:33 PM UTC 24 3513275099 ps
T61 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_cfg_cmd.429398459 Sep 11 12:31:31 PM UTC 24 Sep 11 12:31:40 PM UTC 24 877607375 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_upload.2929603432 Sep 11 12:31:28 PM UTC 24 Sep 11 12:31:46 PM UTC 24 3646143682 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_mailbox.3346341327 Sep 11 12:31:25 PM UTC 24 Sep 11 12:31:51 PM UTC 24 764965001 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode.1670987307 Sep 11 12:31:35 PM UTC 24 Sep 11 12:31:52 PM UTC 24 474650670 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.3261862406 Sep 11 12:30:41 PM UTC 24 Sep 11 12:31:55 PM UTC 24 11559500242 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.4220465844 Sep 11 12:28:48 PM UTC 24 Sep 11 12:32:02 PM UTC 24 78763571471 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_sec_cm.3965333051 Sep 11 12:32:03 PM UTC 24 Sep 11 12:32:06 PM UTC 24 84446433 ps
T86 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_alert_test.3086618308 Sep 11 12:32:07 PM UTC 24 Sep 11 12:32:09 PM UTC 24 13552308 ps
T68 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.2831108285 Sep 11 12:31:47 PM UTC 24 Sep 11 12:32:11 PM UTC 24 3249256050 ps
T352 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_csb_read.1675704128 Sep 11 12:32:10 PM UTC 24 Sep 11 12:32:13 PM UTC 24 29839096 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_all.750029928 Sep 11 12:30:35 PM UTC 24 Sep 11 12:32:13 PM UTC 24 4885505221 ps
T353 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_all.2835438466 Sep 11 12:32:14 PM UTC 24 Sep 11 12:32:16 PM UTC 24 33014531 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.62550282 Sep 11 12:29:04 PM UTC 24 Sep 11 12:32:16 PM UTC 24 40236611163 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.1994958603 Sep 11 12:32:15 PM UTC 24 Sep 11 12:32:17 PM UTC 24 27683326 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_rw.3065965443 Sep 11 12:32:17 PM UTC 24 Sep 11 12:32:22 PM UTC 24 890377417 ps
T70 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_mailbox.3279694661 Sep 11 12:30:22 PM UTC 24 Sep 11 12:32:22 PM UTC 24 144278628810 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.242519297 Sep 11 12:31:41 PM UTC 24 Sep 11 12:32:26 PM UTC 24 8235043252 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.3725903214 Sep 11 12:31:52 PM UTC 24 Sep 11 12:32:32 PM UTC 24 9028612333 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_mailbox.3293523195 Sep 11 12:32:23 PM UTC 24 Sep 11 12:32:33 PM UTC 24 374311934 ps
T354 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_cfg_cmd.1878921482 Sep 11 12:32:32 PM UTC 24 Sep 11 12:32:36 PM UTC 24 108702126 ps
T102 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.3221415612 Sep 11 12:32:18 PM UTC 24 Sep 11 12:32:38 PM UTC 24 17089535140 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_upload.1780239950 Sep 11 12:32:26 PM UTC 24 Sep 11 12:32:42 PM UTC 24 1899355232 ps
T104 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_intercept.2188360611 Sep 11 12:32:23 PM UTC 24 Sep 11 12:32:42 PM UTC 24 2355130545 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.2694986556 Sep 11 12:32:14 PM UTC 24 Sep 11 12:32:43 PM UTC 24 4279335568 ps
T211 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.778660562 Sep 11 12:32:17 PM UTC 24 Sep 11 12:32:44 PM UTC 24 2131145259 ps
T355 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_all.1699673416 Sep 11 12:32:43 PM UTC 24 Sep 11 12:32:45 PM UTC 24 39126607 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_stress_all.3387491874 Sep 11 12:30:42 PM UTC 24 Sep 11 12:32:46 PM UTC 24 8064966575 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_sec_cm.3449690736 Sep 11 12:32:46 PM UTC 24 Sep 11 12:32:49 PM UTC 24 342645095 ps
T167 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_alert_test.4081938442 Sep 11 12:32:47 PM UTC 24 Sep 11 12:32:49 PM UTC 24 58455731 ps
T168 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_csb_read.756033878 Sep 11 12:32:47 PM UTC 24 Sep 11 12:32:49 PM UTC 24 30765325 ps
T149 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode.2364216471 Sep 11 12:32:33 PM UTC 24 Sep 11 12:32:50 PM UTC 24 945573062 ps
T150 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.2506822839 Sep 11 12:32:39 PM UTC 24 Sep 11 12:32:51 PM UTC 24 819268957 ps
T169 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.2686943510 Sep 11 12:32:51 PM UTC 24 Sep 11 12:32:53 PM UTC 24 70169362 ps
T170 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.2658025796 Sep 11 12:32:43 PM UTC 24 Sep 11 12:32:53 PM UTC 24 2746802912 ps
T96 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_rw.2850634615 Sep 11 12:32:52 PM UTC 24 Sep 11 12:32:55 PM UTC 24 27622854 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.1875536277 Sep 11 12:32:53 PM UTC 24 Sep 11 12:33:00 PM UTC 24 779563176 ps
T356 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.1538884724 Sep 11 12:32:50 PM UTC 24 Sep 11 12:33:03 PM UTC 24 3615753241 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.1292766246 Sep 11 12:32:54 PM UTC 24 Sep 11 12:33:04 PM UTC 24 921978403 ps
T228 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_intercept.4051043005 Sep 11 12:32:54 PM UTC 24 Sep 11 12:33:09 PM UTC 24 878448918 ps
T83 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.3180736515 Sep 11 12:32:38 PM UTC 24 Sep 11 12:33:07 PM UTC 24 1247233582 ps
T357 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.2648273982 Sep 11 12:33:07 PM UTC 24 Sep 11 12:33:09 PM UTC 24 29152959 ps
T84 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_upload.3243223271 Sep 11 12:33:01 PM UTC 24 Sep 11 12:33:13 PM UTC 24 798332512 ps
T260 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_cfg_cmd.2395351502 Sep 11 12:33:04 PM UTC 24 Sep 11 12:33:15 PM UTC 24 410737967 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_all.1818204763 Sep 11 12:32:50 PM UTC 24 Sep 11 12:33:20 PM UTC 24 3885182193 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_sec_cm.3839034323 Sep 11 12:33:21 PM UTC 24 Sep 11 12:33:23 PM UTC 24 35629156 ps
T195 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode.1045683936 Sep 11 12:33:04 PM UTC 24 Sep 11 12:33:24 PM UTC 24 959987293 ps
T358 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_alert_test.1312649209 Sep 11 12:33:24 PM UTC 24 Sep 11 12:33:26 PM UTC 24 45894832 ps
T151 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.2615928699 Sep 11 12:33:09 PM UTC 24 Sep 11 12:33:26 PM UTC 24 3501115834 ps
T359 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_csb_read.1283120797 Sep 11 12:33:25 PM UTC 24 Sep 11 12:33:27 PM UTC 24 16532347 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_mailbox.4142535906 Sep 11 12:32:56 PM UTC 24 Sep 11 12:33:28 PM UTC 24 1884337363 ps
T360 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.402411363 Sep 11 12:33:28 PM UTC 24 Sep 11 12:33:31 PM UTC 24 301660322 ps
T349 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_rw.3292876731 Sep 11 12:33:30 PM UTC 24 Sep 11 12:33:33 PM UTC 24 38736784 ps
T361 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.1058588660 Sep 11 12:33:27 PM UTC 24 Sep 11 12:33:37 PM UTC 24 2465846634 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.3222517197 Sep 11 12:33:33 PM UTC 24 Sep 11 12:33:51 PM UTC 24 2233475384 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.2873379 Sep 11 12:30:35 PM UTC 24 Sep 11 12:33:54 PM UTC 24 48782277550 ps
T229 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_intercept.4259155961 Sep 11 12:33:38 PM UTC 24 Sep 11 12:33:58 PM UTC 24 1461343612 ps
T175 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.2289104007 Sep 11 12:33:31 PM UTC 24 Sep 11 12:34:00 PM UTC 24 5460126266 ps
T343 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_all.2546790664 Sep 11 12:33:28 PM UTC 24 Sep 11 12:34:04 PM UTC 24 14115845006 ps
T98 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_upload.628891910 Sep 11 12:33:51 PM UTC 24 Sep 11 12:34:06 PM UTC 24 1172292033 ps
T249 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode.2981186103 Sep 11 12:33:59 PM UTC 24 Sep 11 12:34:06 PM UTC 24 150674943 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.1246112644 Sep 11 12:31:53 PM UTC 24 Sep 11 12:34:10 PM UTC 24 10778654146 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_stress_all.4070490842 Sep 11 12:32:45 PM UTC 24 Sep 11 12:34:12 PM UTC 24 11377160439 ps
T152 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.1558965616 Sep 11 12:34:04 PM UTC 24 Sep 11 12:34:14 PM UTC 24 720375079 ps
T362 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_alert_test.1538046442 Sep 11 12:34:13 PM UTC 24 Sep 11 12:34:15 PM UTC 24 39939397 ps
T363 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_csb_read.2153270636 Sep 11 12:34:15 PM UTC 24 Sep 11 12:34:17 PM UTC 24 53413627 ps
T176 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_cfg_cmd.3506915611 Sep 11 12:33:55 PM UTC 24 Sep 11 12:34:17 PM UTC 24 8942750579 ps
T364 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.3841419139 Sep 11 12:34:19 PM UTC 24 Sep 11 12:34:21 PM UTC 24 122844130 ps
T344 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_rw.738809488 Sep 11 12:34:22 PM UTC 24 Sep 11 12:34:25 PM UTC 24 28412359 ps
T365 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.2029791977 Sep 11 12:34:18 PM UTC 24 Sep 11 12:34:31 PM UTC 24 6277678905 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.1496063403 Sep 11 12:32:44 PM UTC 24 Sep 11 12:34:35 PM UTC 24 17648180175 ps
T136 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_mailbox.184108686 Sep 11 12:33:44 PM UTC 24 Sep 11 12:34:36 PM UTC 24 15744768226 ps
T137 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.2095718901 Sep 11 12:34:32 PM UTC 24 Sep 11 12:34:36 PM UTC 24 148573715 ps
T138 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_all.1905683976 Sep 11 12:34:18 PM UTC 24 Sep 11 12:34:41 PM UTC 24 1333592171 ps
T139 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.1105296061 Sep 11 12:34:25 PM UTC 24 Sep 11 12:34:42 PM UTC 24 17043501471 ps
T140 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_all.651928005 Sep 11 12:31:52 PM UTC 24 Sep 11 12:34:43 PM UTC 24 11908325414 ps
T141 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode.3828007775 Sep 11 12:34:43 PM UTC 24 Sep 11 12:34:49 PM UTC 24 117037881 ps
T142 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_intercept.3137342139 Sep 11 12:34:35 PM UTC 24 Sep 11 12:34:52 PM UTC 24 1086319429 ps
T143 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_cfg_cmd.1828126989 Sep 11 12:34:43 PM UTC 24 Sep 11 12:34:52 PM UTC 24 3079194991 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_stress_all.4109894598 Sep 11 12:29:15 PM UTC 24 Sep 11 12:34:54 PM UTC 24 159034427832 ps
T75 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_mailbox.1883426944 Sep 11 12:34:37 PM UTC 24 Sep 11 12:35:04 PM UTC 24 2382564770 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.4231940680 Sep 11 12:34:50 PM UTC 24 Sep 11 12:35:04 PM UTC 24 734097642 ps
T77 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_alert_test.146714436 Sep 11 12:35:04 PM UTC 24 Sep 11 12:35:06 PM UTC 24 38161474 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_all.1382885748 Sep 11 12:33:10 PM UTC 24 Sep 11 12:35:07 PM UTC 24 17877499741 ps
T79 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_csb_read.2205728756 Sep 11 12:35:05 PM UTC 24 Sep 11 12:35:08 PM UTC 24 54204345 ps
T80 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.1995539135 Sep 11 12:35:11 PM UTC 24 Sep 11 12:35:13 PM UTC 24 75967239 ps
T81 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_rw.3578589626 Sep 11 12:35:14 PM UTC 24 Sep 11 12:35:17 PM UTC 24 148266658 ps
T82 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_upload.2271290205 Sep 11 12:34:37 PM UTC 24 Sep 11 12:35:17 PM UTC 24 24375973498 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.2882407365 Sep 11 12:34:44 PM UTC 24 Sep 11 12:35:20 PM UTC 24 2116307574 ps
T366 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_intercept.3489652179 Sep 11 12:35:21 PM UTC 24 Sep 11 12:35:25 PM UTC 24 74562834 ps
T337 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.1492563137 Sep 11 12:34:54 PM UTC 24 Sep 11 12:35:26 PM UTC 24 1372264181 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.3875774111 Sep 11 12:35:18 PM UTC 24 Sep 11 12:35:29 PM UTC 24 3273863172 ps
T339 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_all.2174531085 Sep 11 12:35:09 PM UTC 24 Sep 11 12:35:29 PM UTC 24 6277720906 ps
T367 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.3514608123 Sep 11 12:35:08 PM UTC 24 Sep 11 12:35:29 PM UTC 24 2637411366 ps
T226 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_upload.2254942945 Sep 11 12:35:27 PM UTC 24 Sep 11 12:35:36 PM UTC 24 13005132996 ps
T99 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_cfg_cmd.1188681856 Sep 11 12:35:29 PM UTC 24 Sep 11 12:35:37 PM UTC 24 350241422 ps
T153 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.273443110 Sep 11 12:35:37 PM UTC 24 Sep 11 12:35:42 PM UTC 24 124633882 ps
T368 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_all.2976623515 Sep 11 12:35:39 PM UTC 24 Sep 11 12:35:46 PM UTC 24 854374006 ps
T90 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_all.2990649995 Sep 11 12:34:05 PM UTC 24 Sep 11 12:35:49 PM UTC 24 23019029697 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.1222574443 Sep 11 12:30:38 PM UTC 24 Sep 11 12:35:49 PM UTC 24 215416869913 ps
T369 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_alert_test.679960431 Sep 11 12:35:50 PM UTC 24 Sep 11 12:35:52 PM UTC 24 54287698 ps
T370 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_csb_read.2022455393 Sep 11 12:35:50 PM UTC 24 Sep 11 12:35:52 PM UTC 24 41109980 ps
T242 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.3633272866 Sep 11 12:35:18 PM UTC 24 Sep 11 12:35:55 PM UTC 24 7211272622 ps
T371 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_all.928165172 Sep 11 12:35:55 PM UTC 24 Sep 11 12:35:58 PM UTC 24 98209167 ps
T372 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.1366921864 Sep 11 12:35:56 PM UTC 24 Sep 11 12:35:59 PM UTC 24 60640805 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_stress_all.398755358 Sep 11 12:34:55 PM UTC 24 Sep 11 12:36:00 PM UTC 24 13486848397 ps
T373 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_rw.1617512956 Sep 11 12:35:59 PM UTC 24 Sep 11 12:36:01 PM UTC 24 24579392 ps
T243 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.3305710030 Sep 11 12:36:00 PM UTC 24 Sep 11 12:36:07 PM UTC 24 5989380373 ps
T374 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode.1624962459 Sep 11 12:35:29 PM UTC 24 Sep 11 12:36:08 PM UTC 24 4439491628 ps
T236 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_intercept.2743759198 Sep 11 12:36:02 PM UTC 24 Sep 11 12:36:12 PM UTC 24 239582331 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.3555346730 Sep 11 12:34:07 PM UTC 24 Sep 11 12:36:12 PM UTC 24 97964098348 ps
T254 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.2036345805 Sep 11 12:36:01 PM UTC 24 Sep 11 12:36:12 PM UTC 24 21905359808 ps
T347 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.3668498005 Sep 11 12:34:53 PM UTC 24 Sep 11 12:36:14 PM UTC 24 3155106072 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_mailbox.558172095 Sep 11 12:35:26 PM UTC 24 Sep 11 12:36:15 PM UTC 24 47517966684 ps
T209 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_upload.3923051609 Sep 11 12:36:09 PM UTC 24 Sep 11 12:36:20 PM UTC 24 1470882895 ps
T375 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.2189140390 Sep 11 12:35:53 PM UTC 24 Sep 11 12:36:21 PM UTC 24 21351049831 ps
T376 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_mailbox.2795101104 Sep 11 12:36:08 PM UTC 24 Sep 11 12:36:21 PM UTC 24 2403480373 ps
T377 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_csb_read.787232830 Sep 11 12:36:22 PM UTC 24 Sep 11 12:36:24 PM UTC 24 18061985 ps
T378 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_alert_test.717808920 Sep 11 12:36:22 PM UTC 24 Sep 11 12:36:24 PM UTC 24 14221416 ps
T248 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode.1078478753 Sep 11 12:36:13 PM UTC 24 Sep 11 12:36:26 PM UTC 24 366910847 ps
T379 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.1204770118 Sep 11 12:36:28 PM UTC 24 Sep 11 12:36:31 PM UTC 24 51787852 ps
T380 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_rw.400664618 Sep 11 12:36:31 PM UTC 24 Sep 11 12:36:34 PM UTC 24 15579348 ps
T259 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_cfg_cmd.2455023021 Sep 11 12:36:12 PM UTC 24 Sep 11 12:36:34 PM UTC 24 5038668976 ps
T341 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_all.4054253557 Sep 11 12:36:27 PM UTC 24 Sep 11 12:36:35 PM UTC 24 1263450123 ps
T246 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.2991126201 Sep 11 12:36:34 PM UTC 24 Sep 11 12:36:42 PM UTC 24 307800978 ps
T381 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.4086093531 Sep 11 12:36:13 PM UTC 24 Sep 11 12:36:42 PM UTC 24 17880166412 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.3291424141 Sep 11 12:36:34 PM UTC 24 Sep 11 12:36:44 PM UTC 24 887599191 ps
T382 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_mailbox.593540714 Sep 11 12:36:43 PM UTC 24 Sep 11 12:36:47 PM UTC 24 103725337 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_stress_all.645404168 Sep 11 12:34:12 PM UTC 24 Sep 11 12:36:48 PM UTC 24 8894513783 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_upload.3440063639 Sep 11 12:36:43 PM UTC 24 Sep 11 12:36:48 PM UTC 24 87937125 ps
T261 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_cfg_cmd.1390933906 Sep 11 12:36:45 PM UTC 24 Sep 11 12:36:49 PM UTC 24 130522680 ps
T213 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_intercept.3578828141 Sep 11 12:36:37 PM UTC 24 Sep 11 12:36:50 PM UTC 24 8533573498 ps
T383 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.1866990560 Sep 11 12:36:25 PM UTC 24 Sep 11 12:36:51 PM UTC 24 55999675474 ps
T384 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode.467468319 Sep 11 12:36:48 PM UTC 24 Sep 11 12:36:52 PM UTC 24 138907962 ps
T385 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.321532662 Sep 11 12:36:49 PM UTC 24 Sep 11 12:36:56 PM UTC 24 1629160451 ps
T386 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_alert_test.2441128487 Sep 11 12:36:55 PM UTC 24 Sep 11 12:36:56 PM UTC 24 16469517 ps
T387 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_alert_test.274906185 Sep 11 12:39:01 PM UTC 24 Sep 11 12:39:03 PM UTC 24 13024329 ps
T388 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_csb_read.1222064591 Sep 11 12:36:58 PM UTC 24 Sep 11 12:37:00 PM UTC 24 19573097 ps
T389 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_all.3950850514 Sep 11 12:37:01 PM UTC 24 Sep 11 12:37:03 PM UTC 24 19970098 ps
T390 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.3317745240 Sep 11 12:37:04 PM UTC 24 Sep 11 12:37:06 PM UTC 24 59974357 ps
T178 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.2844581385 Sep 11 12:34:00 PM UTC 24 Sep 11 12:37:06 PM UTC 24 56109239489 ps
T208 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.2698544094 Sep 11 12:33:13 PM UTC 24 Sep 11 12:37:10 PM UTC 24 35973009087 ps
T391 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.107720419 Sep 11 12:37:01 PM UTC 24 Sep 11 12:37:11 PM UTC 24 4905745572 ps
T392 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_csb_read.2955246239 Sep 11 12:39:03 PM UTC 24 Sep 11 12:39:05 PM UTC 24 270267834 ps
T346 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_rw.2765948913 Sep 11 12:37:07 PM UTC 24 Sep 11 12:37:13 PM UTC 24 370923190 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_intercept.742483718 Sep 11 12:37:11 PM UTC 24 Sep 11 12:37:17 PM UTC 24 97102476 ps
T214 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_all.1995025959 Sep 11 12:36:15 PM UTC 24 Sep 11 12:37:18 PM UTC 24 9938873257 ps
T177 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.3334419631 Sep 11 12:35:31 PM UTC 24 Sep 11 12:37:20 PM UTC 24 18738690854 ps
T393 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_upload.2156661984 Sep 11 12:37:17 PM UTC 24 Sep 11 12:37:21 PM UTC 24 37840710 ps
T394 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_cfg_cmd.2340134671 Sep 11 12:37:18 PM UTC 24 Sep 11 12:37:23 PM UTC 24 406191741 ps
T278 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.393217186 Sep 11 12:37:11 PM UTC 24 Sep 11 12:37:25 PM UTC 24 1066644972 ps
T212 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.1271708552 Sep 11 12:33:16 PM UTC 24 Sep 11 12:37:25 PM UTC 24 25342110557 ps
T395 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.521688442 Sep 11 12:37:23 PM UTC 24 Sep 11 12:37:25 PM UTC 24 11984725 ps
T325 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode.556464751 Sep 11 12:37:21 PM UTC 24 Sep 11 12:37:37 PM UTC 24 754613582 ps
T227 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.1638587503 Sep 11 12:37:07 PM UTC 24 Sep 11 12:37:38 PM UTC 24 16573738481 ps
T396 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_alert_test.4137853124 Sep 11 12:37:39 PM UTC 24 Sep 11 12:37:41 PM UTC 24 73185821 ps
T397 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_csb_read.3478834108 Sep 11 12:37:42 PM UTC 24 Sep 11 12:37:45 PM UTC 24 68085857 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_mailbox.237554589 Sep 11 12:37:14 PM UTC 24 Sep 11 12:37:47 PM UTC 24 6424553431 ps
T398 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.2020939091 Sep 11 12:37:47 PM UTC 24 Sep 11 12:37:50 PM UTC 24 12299347 ps
T204 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_stress_all.409825172 Sep 11 12:31:56 PM UTC 24 Sep 11 12:37:50 PM UTC 24 120240196112 ps
T399 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.3668932449 Sep 11 12:37:24 PM UTC 24 Sep 11 12:37:50 PM UTC 24 8665404568 ps
T400 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.2574082116 Sep 11 12:37:50 PM UTC 24 Sep 11 12:37:53 PM UTC 24 44063410 ps
T401 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_rw.1847775005 Sep 11 12:37:51 PM UTC 24 Sep 11 12:37:54 PM UTC 24 516692358 ps
T250 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_intercept.3099643602 Sep 11 12:37:55 PM UTC 24 Sep 11 12:38:01 PM UTC 24 160395474 ps
T238 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.736412945 Sep 11 12:37:51 PM UTC 24 Sep 11 12:38:06 PM UTC 24 5312248934 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.260018925 Sep 11 12:36:49 PM UTC 24 Sep 11 12:38:12 PM UTC 24 31209508957 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_mailbox.1040447626 Sep 11 12:38:02 PM UTC 24 Sep 11 12:38:16 PM UTC 24 1047579273 ps
T263 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_cfg_cmd.2554219063 Sep 11 12:38:13 PM UTC 24 Sep 11 12:38:17 PM UTC 24 135626699 ps
T402 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode_ignore_cmds.2567435889 Sep 11 12:38:16 PM UTC 24 Sep 11 12:38:18 PM UTC 24 25391906 ps
T403 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_all.1818671077 Sep 11 12:38:19 PM UTC 24 Sep 11 12:38:22 PM UTC 24 15104070 ps
T206 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.4208941473 Sep 11 12:35:43 PM UTC 24 Sep 11 12:38:24 PM UTC 24 13291336453 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.964608566 Sep 11 12:37:54 PM UTC 24 Sep 11 12:38:26 PM UTC 24 6200979148 ps
T144 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.3501520388 Sep 11 12:29:06 PM UTC 24 Sep 11 12:38:29 PM UTC 24 198990204529 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_upload.1448175893 Sep 11 12:38:07 PM UTC 24 Sep 11 12:38:30 PM UTC 24 7875220435 ps
T404 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_alert_test.4175591510 Sep 11 12:38:30 PM UTC 24 Sep 11 12:38:32 PM UTC 24 11556905 ps
T405 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_csb_read.304255496 Sep 11 12:38:31 PM UTC 24 Sep 11 12:38:33 PM UTC 24 72194787 ps
T406 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.1101885274 Sep 11 12:38:18 PM UTC 24 Sep 11 12:38:34 PM UTC 24 1021385675 ps
T407 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.2051240945 Sep 11 12:38:34 PM UTC 24 Sep 11 12:38:36 PM UTC 24 17350981 ps
T408 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.1467271973 Sep 11 12:38:36 PM UTC 24 Sep 11 12:38:39 PM UTC 24 26095599 ps
T207 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_all.1647340699 Sep 11 12:37:26 PM UTC 24 Sep 11 12:38:39 PM UTC 24 46560051283 ps
T409 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_rw.1489008070 Sep 11 12:38:38 PM UTC 24 Sep 11 12:38:41 PM UTC 24 383994274 ps
T231 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_all.118131338 Sep 11 12:36:50 PM UTC 24 Sep 11 12:38:41 PM UTC 24 8096823841 ps
T410 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.2646065285 Sep 11 12:38:40 PM UTC 24 Sep 11 12:38:44 PM UTC 24 134679953 ps
T100 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.2140952616 Sep 11 12:36:13 PM UTC 24 Sep 11 12:38:46 PM UTC 24 9669075946 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_intercept.775653305 Sep 11 12:38:42 PM UTC 24 Sep 11 12:38:49 PM UTC 24 489548201 ps
T279 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.4001699473 Sep 11 12:38:40 PM UTC 24 Sep 11 12:38:49 PM UTC 24 931600636 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_cfg_cmd.291775613 Sep 11 12:38:46 PM UTC 24 Sep 11 12:38:53 PM UTC 24 148359887 ps
T326 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode.2755117724 Sep 11 12:38:15 PM UTC 24 Sep 11 12:38:55 PM UTC 24 2144801645 ps
T345 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_all.3217246784 Sep 11 12:37:48 PM UTC 24 Sep 11 12:38:56 PM UTC 24 8616616834 ps
T411 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_mailbox.2190970400 Sep 11 12:38:42 PM UTC 24 Sep 11 12:39:00 PM UTC 24 4776070728 ps
T412 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.3348811269 Sep 11 12:38:54 PM UTC 24 Sep 11 12:39:00 PM UTC 24 79123958 ps
T340 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_all.1791966111 Sep 11 12:38:34 PM UTC 24 Sep 11 12:39:01 PM UTC 24 2824022172 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_upload.3098163660 Sep 11 12:38:45 PM UTC 24 Sep 11 12:39:02 PM UTC 24 960211347 ps
T91 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.3535586076 Sep 11 12:37:26 PM UTC 24 Sep 11 12:39:02 PM UTC 24 14984422476 ps
T413 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.2570817842 Sep 11 12:39:07 PM UTC 24 Sep 11 12:39:10 PM UTC 24 168372679 ps
T414 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_rw.774244812 Sep 11 12:39:11 PM UTC 24 Sep 11 12:39:19 PM UTC 24 113957582 ps
T415 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.3227076214 Sep 11 12:39:05 PM UTC 24 Sep 11 12:39:27 PM UTC 24 18556283609 ps
T329 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode.3626356854 Sep 11 12:38:50 PM UTC 24 Sep 11 12:39:35 PM UTC 24 8661368521 ps
T416 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_all.2393531448 Sep 11 12:39:06 PM UTC 24 Sep 11 12:39:37 PM UTC 24 16321072590 ps
T221 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.2455670717 Sep 11 12:38:57 PM UTC 24 Sep 11 12:39:38 PM UTC 24 1248396952 ps
T265 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.948541017 Sep 11 12:39:01 PM UTC 24 Sep 11 12:39:39 PM UTC 24 19515141400 ps
T223 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.3373121199 Sep 11 12:36:51 PM UTC 24 Sep 11 12:39:42 PM UTC 24 74926539083 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_intercept.1384802564 Sep 11 12:39:37 PM UTC 24 Sep 11 12:39:43 PM UTC 24 233510217 ps
T194 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_cfg_cmd.1004488235 Sep 11 12:39:40 PM UTC 24 Sep 11 12:39:46 PM UTC 24 342638151 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.40036166 Sep 11 12:39:27 PM UTC 24 Sep 11 12:39:47 PM UTC 24 9773331424 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_cmd_filtering.3178517471 Sep 11 12:39:19 PM UTC 24 Sep 11 12:39:50 PM UTC 24 19287227269 ps
T417 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_read_buffer_direct.988070898 Sep 11 12:39:47 PM UTC 24 Sep 11 12:39:53 PM UTC 24 187823048 ps
T334 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode.3408802035 Sep 11 12:39:42 PM UTC 24 Sep 11 12:40:03 PM UTC 24 5507146828 ps
T172 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_stress_all.239701928 Sep 11 12:40:04 PM UTC 24 Sep 11 12:40:07 PM UTC 24 917916357 ps
T418 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_upload.2123127267 Sep 11 12:39:39 PM UTC 24 Sep 11 12:40:09 PM UTC 24 16202139096 ps
T419 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_alert_test.2092635299 Sep 11 12:40:08 PM UTC 24 Sep 11 12:40:10 PM UTC 24 16128194 ps
T420 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_csb_read.3483744966 Sep 11 12:40:10 PM UTC 24 Sep 11 12:40:12 PM UTC 24 13266758 ps