Group : spi_device_env_pkg::spi_device_env_cov::all_modes_cg
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Group : spi_device_env_pkg::spi_device_env_cov::all_modes_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
72.73 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv


Summary for Group spi_device_env_pkg::spi_device_env_cov::all_modes_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 5 1 4 80.00
Crosses 6 2 4 66.67


Variables for Group spi_device_env_pkg::spi_device_env_cov::all_modes_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_mode 3 1 2 66.67 100 1 1 0
cp_tpm_enabled 2 0 2 100.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::all_modes_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 6 2 4 66.67 100 1 1 0


Summary for Variable cp_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 3 1 2 66.67


Automatically Generated Bins for cp_mode

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
auto[DisabledMode] 0 1 1


Covered bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[FlashMode] 77923 1 T3 310 T4 5 T5 3
auto[PassthroughMode] 54080 1 T6 20 T7 8 T8 6


Summary for Variable cp_tpm_enabled

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_tpm_enabled

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 29526 1 T6 20 T7 8 T8 6
auto[1] 102477 1 T3 310 T4 5 T5 3


Summary for Cross cr_all

Samples crossed: cp_mode cp_tpm_enabled
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 6 2 4 66.67 2


Automatically Generated Cross Bins for cr_all

Element holes
cp_modecp_tpm_enabledCOUNTAT LEASTNUMBERSTATUS
[auto[DisabledMode]] * -- -- 2


Covered bins
cp_mode   cp_tpm_enabled   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[FlashMode] auto[0] 13769 1 T11 2 T38 3 T52 10
auto[FlashMode] auto[1] 64154 1 T3 310 T4 5 T5 3
auto[PassthroughMode] auto[0] 15757 1 T6 20 T7 8 T8 6
auto[PassthroughMode] auto[1] 38323 1 T49 161 T21 418 T66 197