Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	36093	1			T6	10		T7	2		T8	2
auto[SpiFlashAddrCfg]	7964	1			T6	6		T12	2		T37	4
auto[SpiFlashAddr3b]	9361	1			T7	2		T8	2		T11	1
auto[SpiFlashAddr4b]	7673	1			T6	4		T11	1		T12	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34252

1

T6

20

T8

4

T11

2

auto[1]

26839

1

T7

4

T56

2

T47

73

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32341

1

T6

12

T7

2

T8

2

auto[1]

28750

1

T6

8

T7

2

T8

2

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	40777	1			T6	10		T7	2		T8	2
values[1]	1080	1			T47	3		T53	1		T48	4
values[2]	1497	1			T6	2		T37	2		T47	2
values[3]	1443	1			T6	2		T11	1		T12	2
values[4]	1617	1			T18	2		T58	4		T47	1
values[5]	1378	1			T40	4		T58	4		T47	5
values[6]	1607	1			T8	2		T40	4		T57	4
values[7]	1495	1			T6	4		T38	1		T47	6
values[8]	10197	1			T6	2		T7	2		T11	1

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31337

1

T6

20

T7

4

T8

4

auto[1]

29754

1

T11

2

T38

1

T52

10

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

57763

1

T6

18

T7

4

T8

4

write

3328

1

T6

2

T40

2

T47

9

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19797

1

T6

8

T7

2

T11

1

valids[0x1]

41294

1

T6

12

T7

2

T8

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1630	1			T6	2		T7	2		T8	2
internal_process_ops[0x5a]	1616	1			T8	2		T12	2		T18	2
internal_process_ops[0x05]	21557	1			T12	6		T40	18		T60	2
internal_process_ops[0x35]	1719	1			T6	2		T16	8		T18	6
internal_process_ops[0x15]	1695	1			T6	2		T37	2		T40	2
internal_process_ops[0x03]	1029	1			T57	4		T52	1		T47	2
internal_process_ops[0x0b]	1039	1			T11	1		T37	2		T40	4
internal_process_ops[0x3b]	1051	1			T6	2		T56	2		T47	2
internal_process_ops[0x6b]	1082	1			T6	2		T38	1		T52	2
internal_process_ops[0xbb]	1080	1			T6	2		T11	1		T58	2
internal_process_ops[0xeb]	1033	1			T37	2		T40	2		T52	1

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59488

1

T6

20

T7

4

T8

4

auto[1]

1603

1

T47

4

T53

2

T48

5

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58601

1

T6

20

T7

4

T8

4

auto[1]

2490

1

T40

2

T47

7

T48

7

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10564

1

T6

8

T8

2

T12

6

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6347

1

T7

2

T53

15

T48

36

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2222

1

T6

6

T12

2

T37

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1894

1

T53

6

T48

18

T49

8

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2448

1

T8

2

T12

6

T18

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2293

1

T7

2

T56

2

T53

10

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2026

1

T6

4

T12

2

T40

6

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1877

1

T53

6

T48

15

T49

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

131

1

T6

2

T175

2

T176

10

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

109

1

T53

1

T48

2

T21

5

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

101

1

T48

1

T65

2

T177

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

107

1

T21

2

T54

1

T67

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

139

1

T48

1

T21

1

T65

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

66

1

T54

1

T34

1

T42

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

95

1

T49

2

T65

2

T54

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

110

1

T21

2

T65

2

T54

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

118

1

T53

1

T48

1

T65

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

78

1

T48

1

T36

1

T177

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

93

1

T48

1

T21

1

T65

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

116

1

T53

1

T48

1

T65

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

110

1

T40

2

T63

2

T54

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

101

1

T48

1

T21

1

T66

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

79

1

T48

1

T21

1

T67

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

113

1

T49

1

T64

2

T66

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10419

1

T47

52

T55

30

T45

12

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7855

1

T47

27

T55

12

T45

7

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1511

1

T52

1

T47

9

T55

11

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1520

1

T47

16

T55

6

T45

7

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1892

1

T11

1

T47

7

T55

9

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1951

1

T47

19

T55

16

T83

9

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1486

1

T11

1

T38

1

T52

9

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1458

1

T47

6

T55

12

T45

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

119

1

T55

2

T34

1

T90

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

92

1

T47

2

T55

1

T90

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

121

1

T140

1

T34

1

T90

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

128

1

T47

1

T83

3

T140

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

101

1

T55

1

T45

1

T90

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

110

1

T34

5

T78

1

T90

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

101

1

T47

4

T55

1

T34

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

95

1

T83

1

T41

2

T178

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

105

1

T47

1

T34

3

T90

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

96

1

T47

1

T55

2

T34

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

81

1

T55

1

T34

2

T35

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

90

1

T83

1

T90

1

T41

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

116

1

T140

2

T34

2

T41

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

93

1

T55

1

T45

2

T140

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

115

1

T55

4

T34

4

T90

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

99

1

T55

1

T140

2

T34

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3933	1			T59	8		T61	18		T53	15
auto[0]	values[0]	valids[0x1]	15932	1			T6	10		T7	2		T8	2
auto[0]	values[1]	valids[0x1]	515	1			T53	1		T48	4		T49	1
auto[0]	values[2]	valids[0x0]	518	1			T6	2		T48	3		T49	1
auto[0]	values[2]	valids[0x1]	352	1			T37	2		T53	1		T48	1
auto[0]	values[3]	valids[0x0]	513	1			T6	2		T40	2		T53	3
auto[0]	values[3]	valids[0x1]	287	1			T12	2		T40	2		T48	1
auto[0]	values[4]	valids[0x0]	557	1			T53	3		T48	8		T49	1
auto[0]	values[4]	valids[0x1]	338	1			T18	2		T58	4		T53	4
auto[0]	values[5]	valids[0x0]	545	1			T53	1		T48	7		T49	3
auto[0]	values[5]	valids[0x1]	285	1			T40	4		T58	4		T53	3
auto[0]	values[6]	valids[0x0]	587	1			T58	2		T48	4		T49	2
auto[0]	values[6]	valids[0x1]	294	1			T8	2		T40	4		T57	4
auto[0]	values[7]	valids[0x0]	526	1			T6	2		T53	5		T48	5
auto[0]	values[7]	valids[0x1]	321	1			T6	2		T53	1		T49	2
auto[0]	values[8]	valids[0x0]	3700	1			T6	2		T7	2		T12	4
auto[0]	values[8]	valids[0x1]	2134	1			T40	2		T58	2		T60	2
auto[1]	values[0]	valids[0x0]	4021	1			T47	23		T55	19		T45	13
auto[1]	values[0]	valids[0x1]	16891	1			T52	5		T47	73		T55	39
auto[1]	values[1]	valids[0x1]	565	1			T47	3		T55	1		T45	1
auto[1]	values[2]	valids[0x0]	368	1			T47	2		T55	3		T45	2
auto[1]	values[2]	valids[0x1]	259	1			T55	2		T45	1		T140	3
auto[1]	values[3]	valids[0x0]	364	1			T47	2		T149	1		T83	1
auto[1]	values[3]	valids[0x1]	279	1			T11	1		T47	2		T55	1
auto[1]	values[4]	valids[0x0]	439	1			T47	1		T55	6		T83	4
auto[1]	values[4]	valids[0x1]	283	1			T55	3		T140	1		T34	3
auto[1]	values[5]	valids[0x0]	345	1			T47	3		T45	1		T140	3
auto[1]	values[5]	valids[0x1]	203	1			T47	2		T83	1		T34	3
auto[1]	values[6]	valids[0x0]	447	1			T52	1		T55	4		T45	3
auto[1]	values[6]	valids[0x1]	279	1			T47	6		T55	3		T149	1
auto[1]	values[7]	valids[0x0]	362	1			T38	1		T47	2		T83	4
auto[1]	values[7]	valids[0x1]	286	1			T47	4		T55	3		T45	1
auto[1]	values[8]	valids[0x0]	2572	1			T11	1		T52	3		T47	16
auto[1]	values[8]	valids[0x1]	1791	1			T52	1		T47	16		T55	20