Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3416267

1

T6

1

T7

1

T8

149

auto[1]

32537

1

T40

16

T47

35

T48

236

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

836250

1

T6

1

T7

1

T8

149

auto[1]

2612554

1

T12

2772

T16

6662

T18

1024

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	694374	1			T6	1		T7	1		T8	37
auto[524288:1048575]	398571	1			T8	28		T16	4249		T59	26
auto[1048576:1572863]	400074	1			T16	6809		T59	1016		T61	416
auto[1572864:2097151]	361972	1			T8	38		T16	8804		T18	1
auto[2097152:2621439]	411198	1			T8	30		T10	2		T16	593
auto[2621440:3145727]	399602	1			T10	28		T16	2892		T38	418
auto[3145728:3670015]	365961	1			T11	2		T16	2148		T18	2055
auto[3670016:4194303]	417052	1			T8	16		T16	1		T18	8

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2645861

1

T6

1

T7

1

T8

7

auto[1]

802943

1

T8

142

T10

48

T16

20247

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2964630

1

T6

1

T7

1

T8

149

auto[1]

484174

1

T61

857

T47

19

T53

271

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	163257	1			T6	1		T7	1		T8	37
auto[0]	auto[0]	auto[0:524287]	auto[1]	460749	1			T12	2772		T16	616		T18	257
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	85826	1			T8	28		T16	4248		T59	26
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	259975	1			T16	1		T47	3146		T53	750
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	85162	1			T16	3862		T59	1016		T62	252
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	246785	1			T16	2947		T47	2847		T48	5688
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	77092	1			T8	38		T16	5865		T18	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	225451	1			T16	2939		T47	1		T53	2093
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	101915	1			T8	30		T10	2		T16	439
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	255868	1			T16	154		T18	509		T47	256
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	100598	1			T10	28		T16	2888		T38	418
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	233074	1			T16	4		T57	512		T53	2667
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	88937	1			T11	2		T16	2148		T18	1798
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	201739	1			T18	257		T47	256		T53	256
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	115772	1			T8	16		T18	7		T38	2
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	236291	1			T16	1		T18	1		T47	1912
auto[0]	auto[1]	auto[0:524287]	auto[0]	1406	1			T61	415		T21	2		T83	17
auto[0]	auto[1]	auto[0:524287]	auto[1]	62294	1			T21	256		T34	2		T78	6
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1517	1			T45	3		T65	22		T54	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	47715	1			T45	257		T65	5		T54	3
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	2970	1			T61	416		T47	1		T53	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	61713	1			T48	1		T55	256		T21	8687
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	657	1			T61	26		T55	9		T54	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	55454	1			T54	2368		T78	512		T41	260
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	626	1			T45	2		T21	2		T83	5
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	49903	1			T21	1		T65	512		T54	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	2546	1			T47	3		T21	4		T83	14
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	58344	1			T47	4		T21	1		T65	1319
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	2874	1			T53	13		T48	2		T45	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	68108	1			T53	256		T48	3249		T21	4
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	814	1			T33	1		T54	1		T67	5
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	60835	1			T54	1		T34	2453		T67	260
auto[1]	auto[0]	auto[0:524287]	auto[0]	570	1			T40	2		T55	11		T84	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	5309	1			T40	14		T84	34		T98	69
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	506	1			T47	1		T55	3		T54	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2629	1			T54	1		T140	14		T34	19
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	379	1			T47	1		T48	1		T55	13
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2302	1			T47	5		T48	58		T21	12
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	392	1			T47	1		T48	2		T55	5
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2349	1			T47	1		T48	67		T55	247
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	403	1			T48	2		T140	1		T34	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1848	1			T48	88		T65	59		T140	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	405	1			T48	1		T55	5		T54	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2975	1			T48	3		T54	6		T140	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	555	1			T49	2		T55	13		T83	13
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2905	1			T49	2		T78	14		T90	18
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	343	1			T47	3		T49	1		T45	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2269	1			T47	12		T49	4		T45	2
auto[1]	auto[1]	auto[0:524287]	auto[0]	112	1			T83	13		T34	2		T78	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	677	1			T83	1		T34	3		T78	17
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	64	1			T45	1		T65	3		T54	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	339	1			T45	1		T54	1		T208	10
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	101	1			T48	1		T21	2		T90	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	662	1			T48	13		T21	28		T90	3
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	68	1			T42	1		T208	1		T177	11
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	509	1			T42	3		T208	8		T257	11
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	94	1			T21	1		T83	9		T54	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	541	1			T21	36		T54	1		T207	17
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	101	1			T47	1		T21	1		T83	7
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	1559	1			T47	10		T21	7		T54	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	107	1			T21	4		T65	7		T78	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	736	1			T21	84		T78	5		T36	4
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	81	1			T54	1		T41	1		T144	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	647	1			T54	1		T41	14		T144	10

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2144713	1			T6	1		T7	1		T8	7
auto[0]	auto[0]	auto[1]	793778	1			T8	142		T10	48		T16	20247
auto[0]	auto[1]	auto[0]	469320	1			T61	23		T47	8		T53	271
auto[0]	auto[1]	auto[1]	8456	1			T61	834		T21	2		T78	3
auto[1]	auto[0]	auto[0]	25561	1			T40	16		T47	24		T48	222
auto[1]	auto[0]	auto[1]	578	1			T55	4		T83	1		T84	1
auto[1]	auto[1]	auto[0]	6267	1			T47	11		T48	14		T45	2
auto[1]	auto[1]	auto[1]	131	1			T21	3		T83	1		T65	3