Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2651320	1			T1	1		T2	1		T3	1
all_pins[1]	2651320	1			T1	1		T2	1		T3	1
all_pins[2]	2651320	1			T1	1		T2	1		T3	1
all_pins[3]	2651320	1			T1	1		T2	1		T3	1
all_pins[4]	2651320	1			T1	1		T2	1		T3	1
all_pins[5]	2651320	1			T1	1		T2	1		T3	1
all_pins[6]	2651320	1			T1	1		T2	1		T3	1
all_pins[7]	2651320	1			T1	1		T2	1		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	21204634	1			T1	8		T2	8		T3	8
values[0x1]	5926	1			T21	44		T35	2940		T36	26
transitions[0x0=>0x1]	5549	1			T21	33		T35	2937		T36	15
transitions[0x1=>0x0]	5562	1			T21	33		T35	2937		T36	15

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2650995	1			T1	1		T2	1		T3	1
all_pins[0]	values[0x1]	325	1			T21	7		T35	2		T36	1
all_pins[0]	transitions[0x0=>0x1]	255	1			T21	2		T35	2		T36	1
all_pins[0]	transitions[0x1=>0x0]	367	1			T21	7		T35	4		T36	1
all_pins[1]	values[0x0]	2650883	1			T1	1		T2	1		T3	1
all_pins[1]	values[0x1]	437	1			T21	12		T35	4		T36	1
all_pins[1]	transitions[0x0=>0x1]	401	1			T21	11		T35	4		T36	1
all_pins[1]	transitions[0x1=>0x0]	298	1			T21	2		T35	5		T36	4
all_pins[2]	values[0x0]	2650986	1			T1	1		T2	1		T3	1
all_pins[2]	values[0x1]	334	1			T21	3		T35	5		T36	4
all_pins[2]	transitions[0x0=>0x1]	291	1			T35	4		T36	2		T173	6
all_pins[2]	transitions[0x1=>0x0]	150	1			T21	3		T35	2		T36	2
all_pins[3]	values[0x0]	2651127	1			T1	1		T2	1		T3	1
all_pins[3]	values[0x1]	193	1			T21	6		T35	3		T36	4
all_pins[3]	transitions[0x0=>0x1]	158	1			T21	5		T35	3		T36	1
all_pins[3]	transitions[0x1=>0x0]	159	1			T21	4		T35	2		T36	3
all_pins[4]	values[0x0]	2651126	1			T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	194	1			T21	5		T35	2		T36	6
all_pins[4]	transitions[0x0=>0x1]	148	1			T21	4		T35	2		T36	3
all_pins[4]	transitions[0x1=>0x0]	1106	1			T21	1		T35	4		T172	4
all_pins[5]	values[0x0]	2650168	1			T1	1		T2	1		T3	1
all_pins[5]	values[0x1]	1152	1			T21	2		T35	4		T36	3
all_pins[5]	transitions[0x0=>0x1]	1112	1			T21	2		T35	3		T172	4
all_pins[5]	transitions[0x1=>0x0]	3059	1			T21	7		T35	2915		T36	3
all_pins[6]	values[0x0]	2648221	1			T1	1		T2	1		T3	1
all_pins[6]	values[0x1]	3099	1			T21	7		T35	2916		T36	6
all_pins[6]	transitions[0x0=>0x1]	3057	1			T21	7		T35	2915		T36	6
all_pins[6]	transitions[0x1=>0x0]	150	1			T21	2		T35	3		T36	1
all_pins[7]	values[0x0]	2651128	1			T1	1		T2	1		T3	1
all_pins[7]	values[0x1]	192	1			T21	2		T35	4		T36	1
all_pins[7]	transitions[0x0=>0x1]	127	1			T21	2		T35	4		T36	1
all_pins[7]	transitions[0x1=>0x0]	273	1			T21	7		T35	2		T36	1