Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18112

1

T6

20

T8

4

T12

16

auto[1]

13225

1

T7

4

T56

2

T53

38

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3972	1			T7	4		T12	16		T53	20
values[1]	3581	1			T8	4		T18	8		T59	8
values[2]	4169	1			T16	10		T53	20		T48	119
values[3]	3230	1			T58	14		T48	60		T49	26
values[4]	3752	1			T61	18		T53	20		T21	129
values[5]	4238	1			T37	6		T56	2		T40	40
values[6]	3940	1			T6	20		T60	14		T48	20
values[7]	4455	1			T62	12		T48	79		T70	22

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3673	1			T57	6		T61	18		T53	20
values[1]	3922	1			T60	14		T48	102		T49	23
values[2]	4294	1			T6	20		T8	4		T18	8
values[3]	3388	1			T53	40		T21	103		T175	20
values[4]	3498	1			T12	16		T16	10		T37	6
values[5]	4765	1			T7	4		T40	40		T211	22
values[6]	4599	1			T56	2		T48	159		T21	121
values[7]	3198	1			T48	20		T49	26		T102	12

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	214	1			T144	17		T258	10		T162	10
auto[0]	values[0]	values[1]	344	1			T259	4		T36	13		T212	53
auto[0]	values[0]	values[2]	294	1			T65	13		T177	9		T251	22
auto[0]	values[0]	values[3]	341	1			T53	9		T21	67		T66	10
auto[0]	values[0]	values[4]	267	1			T12	16		T214	13		T235	8
auto[0]	values[0]	values[5]	243	1			T260	6		T261	10		T258	9
auto[0]	values[0]	values[6]	285	1			T177	13		T206	24		T101	16
auto[0]	values[0]	values[7]	337	1			T177	21		T262	98		T233	12
auto[0]	values[1]	values[0]	194	1			T57	6		T36	8		T212	10
auto[0]	values[1]	values[1]	261	1			T65	8		T34	14		T226	21
auto[0]	values[1]	values[2]	627	1			T8	4		T18	8		T59	8
auto[0]	values[1]	values[3]	156	1			T238	14		T100	23		T198	13
auto[0]	values[1]	values[4]	173	1			T212	13		T231	10		T100	7
auto[0]	values[1]	values[5]	265	1			T34	12		T263	4		T221	11
auto[0]	values[1]	values[6]	307	1			T98	89		T36	34		T214	5
auto[0]	values[1]	values[7]	182	1			T199	12		T258	13		T162	15
auto[0]	values[2]	values[0]	359	1			T54	33		T204	9		T203	15
auto[0]	values[2]	values[1]	319	1			T49	14		T21	78		T65	9
auto[0]	values[2]	values[2]	147	1			T33	12		T36	9		T177	14
auto[0]	values[2]	values[3]	241	1			T53	12		T67	16		T209	8
auto[0]	values[2]	values[4]	213	1			T16	10		T228	12		T144	8
auto[0]	values[2]	values[5]	439	1			T246	12		T255	159		T199	8
auto[0]	values[2]	values[6]	466	1			T48	107		T214	8		T212	30
auto[0]	values[2]	values[7]	235	1			T204	10		T205	53		T233	10
auto[0]	values[3]	values[0]	188	1			T264	8		T258	12		T196	8
auto[0]	values[3]	values[1]	309	1			T48	10		T144	26		T160	9
auto[0]	values[3]	values[2]	198	1			T229	20		T243	14		T265	12
auto[0]	values[3]	values[3]	145	1			T144	10		T258	15		T201	25
auto[0]	values[3]	values[4]	172	1			T58	14		T204	13		T235	15
auto[0]	values[3]	values[5]	277	1			T258	6		T266	9		T267	21
auto[0]	values[3]	values[6]	291	1			T48	10		T21	15		T144	31
auto[0]	values[3]	values[7]	185	1			T48	12		T49	12		T54	13
auto[0]	values[4]	values[0]	270	1			T61	18		T54	13		T99	18
auto[0]	values[4]	values[1]	298	1			T65	11		T36	11		T268	12
auto[0]	values[4]	values[2]	151	1			T65	10		T42	7		T206	11
auto[0]	values[4]	values[3]	188	1			T21	15		T206	13		T202	10
auto[0]	values[4]	values[4]	234	1			T53	11		T144	16		T215	11
auto[0]	values[4]	values[5]	286	1			T236	16		T222	11		T233	7
auto[0]	values[4]	values[6]	505	1			T21	14		T54	18		T42	12
auto[0]	values[4]	values[7]	112	1			T269	10		T199	12		T230	24
auto[0]	values[5]	values[0]	373	1			T53	10		T177	6		T204	14
auto[0]	values[5]	values[1]	212	1			T48	74		T204	19		T100	10
auto[0]	values[5]	values[2]	267	1			T49	15		T270	10		T258	14
auto[0]	values[5]	values[3]	243	1			T54	21		T204	14		T271	4
auto[0]	values[5]	values[4]	227	1			T37	6		T71	10		T65	12
auto[0]	values[5]	values[5]	604	1			T40	40		T211	22		T139	6
auto[0]	values[5]	values[6]	304	1			T36	6		T177	14		T204	54
auto[0]	values[5]	values[7]	172	1			T54	12		T204	10		T198	10
auto[0]	values[6]	values[0]	288	1			T104	6		T176	10		T67	10
auto[0]	values[6]	values[1]	189	1			T60	14		T42	13		T222	17
auto[0]	values[6]	values[2]	571	1			T6	20		T42	22		T258	10
auto[0]	values[6]	values[3]	184	1			T144	9		T199	12		T272	10
auto[0]	values[6]	values[4]	187	1			T136	14		T142	4		T233	15
auto[0]	values[6]	values[5]	282	1			T250	14		T206	11		T231	11
auto[0]	values[6]	values[6]	288	1			T48	12		T36	13		T214	8
auto[0]	values[6]	values[7]	233	1			T54	12		T82	18		T268	5
auto[0]	values[7]	values[0]	338	1			T63	14		T177	14		T100	17
auto[0]	values[7]	values[1]	240	1			T273	10		T212	14		T202	33
auto[0]	values[7]	values[2]	450	1			T48	75		T70	22		T21	10
auto[0]	values[7]	values[3]	334	1			T175	20		T42	9		T36	14
auto[0]	values[7]	values[4]	449	1			T62	12		T54	13		T34	13
auto[0]	values[7]	values[5]	383	1			T66	16		T75	12		T214	12
auto[0]	values[7]	values[6]	272	1			T67	16		T162	19		T274	6
auto[0]	values[7]	values[7]	304	1			T21	20		T275	2		T233	23
auto[1]	values[0]	values[0]	178	1			T144	6		T258	10		T162	10
auto[1]	values[0]	values[1]	159	1			T36	7		T212	5		T204	10
auto[1]	values[0]	values[2]	280	1			T65	7		T177	11		T251	10
auto[1]	values[0]	values[3]	240	1			T53	11		T21	8		T66	13
auto[1]	values[0]	values[4]	190	1			T214	7		T235	15		T162	6
auto[1]	values[0]	values[5]	250	1			T7	4		T258	11		T162	30
auto[1]	values[0]	values[6]	124	1			T177	7		T206	6		T215	5
auto[1]	values[0]	values[7]	226	1			T177	19		T233	13		T224	8
auto[1]	values[1]	values[0]	137	1			T36	12		T212	21		T235	11
auto[1]	values[1]	values[1]	217	1			T65	12		T34	6		T144	6
auto[1]	values[1]	values[2]	203	1			T48	26		T177	18		T202	9
auto[1]	values[1]	values[3]	145	1			T276	14		T100	17		T198	7
auto[1]	values[1]	values[4]	117	1			T212	7		T231	10		T100	13
auto[1]	values[1]	values[5]	222	1			T34	8		T221	9		T199	9
auto[1]	values[1]	values[6]	211	1			T36	12		T214	15		T212	42
auto[1]	values[1]	values[7]	164	1			T199	8		T258	7		T162	5
auto[1]	values[2]	values[0]	174	1			T54	13		T204	11		T203	5
auto[1]	values[2]	values[1]	276	1			T49	9		T21	17		T65	11
auto[1]	values[2]	values[2]	196	1			T33	8		T36	11		T177	6
auto[1]	values[2]	values[3]	183	1			T53	8		T67	4		T36	7
auto[1]	values[2]	values[4]	383	1			T254	10		T144	25		T231	12
auto[1]	values[2]	values[5]	133	1			T199	12		T222	12		T198	9
auto[1]	values[2]	values[6]	262	1			T48	12		T214	12		T212	10
auto[1]	values[2]	values[7]	143	1			T204	10		T277	6		T233	26
auto[1]	values[3]	values[0]	246	1			T278	18		T258	8		T196	12
auto[1]	values[3]	values[1]	258	1			T48	10		T144	14		T160	14
auto[1]	values[3]	values[2]	124	1			T265	9		T222	11		T219	9
auto[1]	values[3]	values[3]	230	1			T144	10		T279	16		T258	5
auto[1]	values[3]	values[4]	95	1			T204	12		T235	9		T266	3
auto[1]	values[3]	values[5]	160	1			T258	14		T266	11		T267	21
auto[1]	values[3]	values[6]	117	1			T48	10		T21	5		T144	15
auto[1]	values[3]	values[7]	235	1			T48	8		T49	14		T102	12
auto[1]	values[4]	values[0]	200	1			T256	22		T54	8		T162	9
auto[1]	values[4]	values[1]	324	1			T65	9		T36	17		T268	8
auto[1]	values[4]	values[2]	145	1			T65	10		T42	13		T206	9
auto[1]	values[4]	values[3]	120	1			T21	13		T206	7		T202	10
auto[1]	values[4]	values[4]	202	1			T53	9		T144	24		T215	25
auto[1]	values[4]	values[5]	249	1			T222	10		T233	54		T174	8
auto[1]	values[4]	values[6]	397	1			T21	87		T54	12		T42	8
auto[1]	values[4]	values[7]	71	1			T199	11		T225	7		T280	11
auto[1]	values[5]	values[0]	264	1			T53	10		T177	14		T204	6
auto[1]	values[5]	values[1]	91	1			T48	8		T204	5		T281	18
auto[1]	values[5]	values[2]	177	1			T49	5		T258	6		T162	11
auto[1]	values[5]	values[3]	207	1			T54	4		T204	6		T200	66
auto[1]	values[5]	values[4]	170	1			T65	8		T34	10		T212	6
auto[1]	values[5]	values[5]	439	1			T42	8		T214	38		T282	24
auto[1]	values[5]	values[6]	263	1			T56	2		T36	63		T177	6
auto[1]	values[5]	values[7]	225	1			T54	8		T204	17		T198	129
auto[1]	values[6]	values[0]	134	1			T67	10		T100	5		T219	7
auto[1]	values[6]	values[1]	265	1			T42	13		T283	18		T222	12
auto[1]	values[6]	values[2]	232	1			T64	6		T42	44		T258	10
auto[1]	values[6]	values[3]	129	1			T144	12		T199	8		T272	10
auto[1]	values[6]	values[4]	130	1			T233	6		T198	3		T145	10
auto[1]	values[6]	values[5]	385	1			T206	41		T231	9		T235	7
auto[1]	values[6]	values[6]	309	1			T48	8		T36	58		T214	111
auto[1]	values[6]	values[7]	134	1			T54	15		T268	15		T144	11
auto[1]	values[7]	values[0]	116	1			T177	6		T100	23		T251	7
auto[1]	values[7]	values[1]	160	1			T242	16		T212	6		T202	11
auto[1]	values[7]	values[2]	232	1			T48	4		T21	28		T54	13
auto[1]	values[7]	values[3]	302	1			T42	11		T36	83		T251	15
auto[1]	values[7]	values[4]	289	1			T54	9		T34	7		T212	8
auto[1]	values[7]	values[5]	148	1			T66	5		T214	8		T100	12
auto[1]	values[7]	values[6]	198	1			T67	4		T162	8		T284	38
auto[1]	values[7]	values[7]	240	1			T21	14		T233	12		T284	11