Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

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Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	441	1			T48	2		T49	4		T21	2
auto[ReadAddrCrossIntoMailbox]	280	1			T48	4		T49	1		T21	2
auto[ReadAddrCrossOutOfMailbox]	350	1			T48	8		T49	6		T21	3
auto[ReadAddrCrossAllMailbox]	212	1			T48	2		T49	1		T65	2
auto[ReadAddrOutsideMailbox]	3560	1			T6	6		T37	4		T56	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2339

1

T6

3

T37

2

T56

1

auto[1]

2504

1

T6

3

T37

2

T56

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	808	1			T57	4		T53	3		T48	8
read_ops[0x0b]	775	1			T37	2		T40	4		T58	4
read_ops[0x3b]	828	1			T6	2		T56	2		T53	1
read_ops[0x6b]	834	1			T6	2		T53	5		T48	7
read_ops[0xbb]	814	1			T6	2		T58	2		T53	1
read_ops[0xeb]	784	1			T37	2		T40	2		T53	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	44	1			T48	1		T21	1		T54	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T67	1		T236	2		T286	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T54	1		T75	1		T214	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T48	1		T75	1		T258	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	34	1			T21	1		T65	1		T54	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T34	1		T287	1		T144	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T206	1		T202	1		T235	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T48	2		T42	1		T196	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	270	1			T57	2		T48	2		T21	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	317	1			T57	2		T53	3		T48	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T65	2		T36	2		T250	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	45	1			T42	1		T36	1		T214	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T75	1		T36	1		T100	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T75	1		T206	1		T222	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T49	2		T258	1		T288	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	32	1			T21	1		T212	1		T100	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T34	1		T75	1		T204	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T65	1		T75	1		T144	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	264	1			T37	1		T40	2		T58	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	305	1			T37	1		T40	2		T58	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T228	1		T65	1		T100	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T49	2		T228	1		T54	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T54	1		T214	1		T212	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T54	1		T268	1		T144	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	31	1			T48	3		T33	1		T212	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T49	1		T36	1		T258	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T54	1		T258	1		T215	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T49	1		T144	1		T235	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	289	1			T6	1		T56	1		T53	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	334	1			T6	1		T56	1		T48	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T48	1		T21	1		T250	3
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T214	1		T250	3		T144	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T65	1		T206	1		T266	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T48	1		T144	1		T202	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T49	1		T206	1		T222	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	39	1			T67	3		T212	1		T204	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T177	2		T206	1		T265	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T202	1		T196	1		T289	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	313	1			T6	1		T53	3		T48	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	304	1			T6	1		T53	2		T48	3
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T75	1		T36	2		T144	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T65	1		T34	1		T75	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T36	1		T204	1		T206	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	33	1			T21	2		T67	1		T268	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T48	1		T65	1		T36	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T48	2		T21	1		T214	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T251	1		T215	1		T210	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T214	1		T144	1		T258	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	305	1			T6	1		T58	1		T48	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	302	1			T6	1		T58	1		T53	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	42	1			T49	2		T229	1		T204	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T229	1		T144	2		T231	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T49	1		T67	1		T36	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	31	1			T48	2		T33	1		T36	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	35	1			T48	1		T49	1		T54	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	33	1			T48	1		T49	1		T214	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T212	1		T100	1		T251	4
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T65	1		T215	1		T288	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	279	1			T37	1		T40	1		T49	3
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	278	1			T37	1		T40	1		T53	2