Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2899	1			T8	4		T58	14		T269	10
values[1]	4322	1			T16	10		T53	20		T71	10
values[2]	3600	1			T48	20		T21	75		T63	14
values[3]	4074	1			T7	4		T48	221		T229	20
values[4]	4003	1			T6	20		T18	8		T61	18
values[5]	4721	1			T59	8		T56	2		T60	14
values[6]	3725	1			T37	6		T40	40		T57	6
values[7]	3993	1			T12	16		T53	60		T48	79

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3729	1			T6	20		T58	14		T49	20
values[1]	4145	1			T12	16		T60	14		T48	102
values[2]	4509	1			T37	6		T61	18		T62	12
values[3]	3890	1			T16	10		T49	23		T228	12
values[4]	4284	1			T8	4		T59	8		T40	40
values[5]	3492	1			T53	20		T48	20		T102	12
values[6]	3801	1			T7	4		T18	8		T56	2
values[7]	3487	1			T57	6		T53	20		T48	135

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30537

1

T6

20

T7

4

T8

4

auto[1]

800

1

T53

2

T48

5

T49

1

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	358	1			T58	14		T54	25		T177	18
auto[0]	values[0]	values[1]	486	1			T212	83		T144	20		T290	6
auto[0]	values[0]	values[2]	276	1			T204	23		T281	16		T174	65
auto[0]	values[0]	values[3]	402	1			T269	10		T212	20		T291	8
auto[0]	values[0]	values[4]	483	1			T8	4		T144	52		T222	49
auto[0]	values[0]	values[5]	346	1			T36	39		T214	19		T258	20
auto[0]	values[0]	values[6]	237	1			T212	33		T251	29		T292	6
auto[0]	values[0]	values[7]	234	1			T42	21		T259	4		T144	20
auto[0]	values[1]	values[0]	557	1			T177	20		T194	12		T202	71
auto[0]	values[1]	values[1]	451	1			T65	20		T66	21		T54	25
auto[0]	values[1]	values[2]	871	1			T33	20		T213	8		T204	23
auto[0]	values[1]	values[3]	364	1			T16	10		T162	18		T284	59
auto[0]	values[1]	values[4]	380	1			T231	18		T100	19		T196	18
auto[0]	values[1]	values[5]	564	1			T53	19		T270	10		T100	39
auto[0]	values[1]	values[6]	343	1			T71	10		T139	6		T293	2
auto[0]	values[1]	values[7]	653	1			T54	20		T209	8		T177	20
auto[0]	values[2]	values[0]	376	1			T175	20		T236	16		T251	24
auto[0]	values[2]	values[1]	359	1			T54	22		T202	65		T277	6
auto[0]	values[2]	values[2]	685	1			T177	19		T271	4		T196	97
auto[0]	values[2]	values[3]	379	1			T34	20		T204	20		T294	10
auto[0]	values[2]	values[4]	446	1			T100	20		T202	42		T251	21
auto[0]	values[2]	values[5]	213	1			T36	20		T206	20		T295	12
auto[0]	values[2]	values[6]	561	1			T21	75		T65	20		T36	20
auto[0]	values[2]	values[7]	486	1			T48	19		T63	14		T65	20
auto[0]	values[3]	values[0]	321	1			T54	29		T226	21		T287	2
auto[0]	values[3]	values[1]	644	1			T48	82		T229	20		T34	19
auto[0]	values[3]	values[2]	571	1			T48	118		T296	8		T203	20
auto[0]	values[3]	values[3]	640	1			T42	24		T268	18		T297	16
auto[0]	values[3]	values[4]	622	1			T48	20		T144	28		T239	10
auto[0]	values[3]	values[5]	324	1			T42	41		T212	20		T196	44
auto[0]	values[3]	values[6]	549	1			T7	4		T160	20		T272	170
auto[0]	values[3]	values[7]	304	1			T235	20		T274	6		T266	40
auto[0]	values[4]	values[0]	431	1			T6	20		T49	20		T84	44
auto[0]	values[4]	values[1]	691	1			T21	100		T67	20		T243	14
auto[0]	values[4]	values[2]	431	1			T61	18		T62	12		T64	4
auto[0]	values[4]	values[3]	528	1			T228	12		T136	14		T255	159
auto[0]	values[4]	values[4]	429	1			T42	20		T231	22		T100	40
auto[0]	values[4]	values[5]	365	1			T102	12		T142	4		T99	18
auto[0]	values[4]	values[6]	792	1			T18	8		T21	66		T66	21
auto[0]	values[4]	values[7]	226	1			T210	18		T174	20		T198	28
auto[0]	values[5]	values[0]	625	1			T65	18		T204	64		T250	14
auto[0]	values[5]	values[1]	478	1			T60	14		T48	20		T36	19
auto[0]	values[5]	values[2]	635	1			T21	60		T54	20		T36	26
auto[0]	values[5]	values[3]	404	1			T49	22		T54	25		T177	19
auto[0]	values[5]	values[4]	954	1			T59	8		T21	33		T65	18
auto[0]	values[5]	values[5]	713	1			T48	20		T104	6		T21	20
auto[0]	values[5]	values[6]	401	1			T56	2		T34	20		T273	10
auto[0]	values[5]	values[7]	418	1			T48	34		T177	20		T204	19
auto[0]	values[6]	values[0]	520	1			T42	20		T238	14		T235	22
auto[0]	values[6]	values[1]	518	1			T49	26		T176	10		T54	22
auto[0]	values[6]	values[2]	359	1			T37	6		T212	40		T199	20
auto[0]	values[6]	values[3]	554	1			T256	22		T75	12		T144	21
auto[0]	values[6]	values[4]	428	1			T40	40		T211	22		T276	14
auto[0]	values[6]	values[5]	499	1			T34	21		T206	42		T144	21
auto[0]	values[6]	values[6]	361	1			T70	22		T21	27		T214	20
auto[0]	values[6]	values[7]	392	1			T57	6		T265	19		T298	8
auto[0]	values[7]	values[0]	447	1			T143	10		T227	22		T201	20
auto[0]	values[7]	values[1]	400	1			T12	16		T36	97		T206	18
auto[0]	values[7]	values[2]	576	1			T53	20		T285	4		T54	20
auto[0]	values[7]	values[3]	519	1			T242	16		T204	20		T299	18
auto[0]	values[7]	values[4]	430	1			T214	115		T204	62		T279	12
auto[0]	values[7]	values[5]	372	1			T260	6		T212	30		T144	26
auto[0]	values[7]	values[6]	478	1			T53	20		T265	20		T300	8
auto[0]	values[7]	values[7]	678	1			T53	19		T48	78		T42	20
auto[1]	values[0]	values[0]	6	1			T54	2		T177	2		T201	2
auto[1]	values[0]	values[1]	19	1			T212	2		T290	2		T162	1
auto[1]	values[0]	values[2]	19	1			T281	2		T174	3		T72	1
auto[1]	values[0]	values[3]	7	1			T215	2		T201	1		T301	2
auto[1]	values[0]	values[4]	8	1			T144	1		T302	2		T74	2
auto[1]	values[0]	values[5]	10	1			T36	1		T214	1		T222	1
auto[1]	values[0]	values[6]	5	1			T212	1		T251	3		T303	1
auto[1]	values[0]	values[7]	3	1			T200	1		T304	2		-	-
auto[1]	values[1]	values[0]	20	1			T202	1		T267	4		T305	2
auto[1]	values[1]	values[1]	14	1			T66	2		T67	3		T224	5
auto[1]	values[1]	values[2]	20	1			T204	1		T100	1		T244	1
auto[1]	values[1]	values[3]	12	1			T162	2		T284	5		T266	1
auto[1]	values[1]	values[4]	18	1			T231	2		T100	1		T196	2
auto[1]	values[1]	values[5]	23	1			T53	1		T100	1		T282	6
auto[1]	values[1]	values[6]	8	1			T162	2		T245	1		T222	2
auto[1]	values[1]	values[7]	24	1			T212	2		T204	1		T231	9
auto[1]	values[2]	values[0]	9	1			T201	2		T267	2		T306	2
auto[1]	values[2]	values[1]	22	1			T202	5		T199	4		T307	2
auto[1]	values[2]	values[2]	12	1			T177	1		T196	2		T284	1
auto[1]	values[2]	values[3]	10	1			T308	2		T309	2		T303	2
auto[1]	values[2]	values[4]	10	1			T202	2		T310	2		T233	2
auto[1]	values[2]	values[5]	6	1			T235	1		T219	2		T311	2
auto[1]	values[2]	values[6]	11	1			T258	1		T215	1		T266	1
auto[1]	values[2]	values[7]	15	1			T48	1		T54	2		T245	3
auto[1]	values[3]	values[0]	11	1			T54	1		T258	1		T305	1
auto[1]	values[3]	values[1]	13	1			T34	1		T235	1		T72	1
auto[1]	values[3]	values[2]	13	1			T48	1		T200	5		T284	1
auto[1]	values[3]	values[3]	19	1			T42	2		T268	2		T233	1
auto[1]	values[3]	values[4]	16	1			T144	3		T162	1		T312	2
auto[1]	values[3]	values[5]	9	1			T42	4		T196	1		T251	1
auto[1]	values[3]	values[6]	10	1			T272	1		T219	1		T217	1
auto[1]	values[3]	values[7]	8	1			T219	2		T313	1		T305	1
auto[1]	values[4]	values[0]	12	1			T258	3		T314	1		T315	3
auto[1]	values[4]	values[1]	14	1			T21	1		T177	5		T198	3
auto[1]	values[4]	values[2]	7	1			T64	2		T36	2		T306	1
auto[1]	values[4]	values[3]	24	1			T258	1		T162	3		T174	1
auto[1]	values[4]	values[4]	13	1			T231	1		T196	4		T163	3
auto[1]	values[4]	values[5]	8	1			T231	2		T316	2		T163	1
auto[1]	values[4]	values[6]	25	1			T21	6		T204	3		T144	1
auto[1]	values[4]	values[7]	7	1			T210	2		T317	3		T318	2
auto[1]	values[5]	values[0]	18	1			T65	2		T204	1		T251	1
auto[1]	values[5]	values[1]	7	1			T36	1		T235	1		T316	4
auto[1]	values[5]	values[2]	17	1			T21	2		T54	1		T36	2
auto[1]	values[5]	values[3]	10	1			T49	1		T177	1		T163	1
auto[1]	values[5]	values[4]	19	1			T65	2		T221	2		T199	2
auto[1]	values[5]	values[5]	12	1			T177	3		T284	1		T301	1
auto[1]	values[5]	values[6]	5	1			T251	2		T200	1		T145	1
auto[1]	values[5]	values[7]	5	1			T48	2		T204	1		T319	1
auto[1]	values[6]	values[0]	11	1			T235	2		T200	1		T224	1
auto[1]	values[6]	values[1]	14	1			T278	10		T266	1		T311	3
auto[1]	values[6]	values[2]	6	1			T316	2		T301	3		T320	1
auto[1]	values[6]	values[3]	12	1			T202	1		T321	1		T322	1
auto[1]	values[6]	values[4]	15	1			T212	1		T162	6		T145	5
auto[1]	values[6]	values[5]	14	1			T34	1		T206	2		T144	2
auto[1]	values[6]	values[6]	12	1			T21	1		T160	1		T145	2
auto[1]	values[6]	values[7]	10	1			T265	1		T222	3		T316	2
auto[1]	values[7]	values[0]	7	1			T174	2		T72	1		T323	2
auto[1]	values[7]	values[1]	15	1			T206	2		T317	4		T324	1
auto[1]	values[7]	values[2]	11	1			T198	1		T267	2		T313	2
auto[1]	values[7]	values[3]	6	1			T266	1		T145	2		T163	2
auto[1]	values[7]	values[4]	13	1			T214	4		T204	3		T279	4
auto[1]	values[7]	values[5]	14	1			T212	1		T210	1		T225	3
auto[1]	values[7]	values[6]	3	1			T265	1		T311	2		-	-
auto[1]	values[7]	values[7]	24	1			T53	1		T48	1		T177	3