Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	821	1			T21	20		T34	4		T35	17
all_values[1]	821	1			T21	20		T34	4		T35	17
all_values[2]	821	1			T21	20		T34	4		T35	17
all_values[3]	821	1			T21	20		T34	4		T35	17
all_values[4]	821	1			T21	20		T34	4		T35	17
all_values[5]	821	1			T21	20		T34	4		T35	17
all_values[6]	821	1			T21	20		T34	4		T35	17
all_values[7]	821	1			T21	20		T34	4		T35	17

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3367

1

T21

80

T34

23

T35

68

auto[1]

3201

1

T21

80

T34

9

T35

68

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2697

1

T21

56

T34

16

T35

57

auto[1]

3871

1

T21

104

T34

16

T35

79

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3791

1

T21

89

T34

20

T35

74

auto[1]

2777

1

T21

71

T34

12

T35

62

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	164	1			T21	4		T34	2		T35	4
all_values[0]	auto[0]	auto[0]	auto[1]	67	1			T21	2		T35	2		T36	2
all_values[0]	auto[0]	auto[1]	auto[0]	147	1			T21	2		T34	2		T35	5
all_values[0]	auto[0]	auto[1]	auto[1]	89	1			T21	2		T36	1		T171	3
all_values[0]	auto[1]	auto[0]	auto[1]	162	1			T21	4		T35	2		T172	3
all_values[0]	auto[1]	auto[1]	auto[1]	192	1			T21	6		T35	4		T36	2
all_values[1]	auto[0]	auto[0]	auto[0]	148	1			T34	1		T35	3		T36	4
all_values[1]	auto[0]	auto[0]	auto[1]	77	1			T34	1		T35	3		T36	1
all_values[1]	auto[0]	auto[1]	auto[0]	191	1			T21	3		T34	1		T35	2
all_values[1]	auto[0]	auto[1]	auto[1]	78	1			T21	8		T172	1		T171	3
all_values[1]	auto[1]	auto[0]	auto[1]	184	1			T21	3		T34	1		T35	5
all_values[1]	auto[1]	auto[1]	auto[1]	143	1			T21	6		T35	4		T172	2
all_values[2]	auto[0]	auto[0]	auto[0]	178	1			T21	6		T35	3		T172	2
all_values[2]	auto[0]	auto[0]	auto[1]	68	1			T21	4		T34	1		T35	1
all_values[2]	auto[0]	auto[1]	auto[0]	143	1			T21	1		T35	4		T172	5
all_values[2]	auto[0]	auto[1]	auto[1]	91	1			T35	2		T36	2		T173	6
all_values[2]	auto[1]	auto[0]	auto[1]	181	1			T21	4		T34	3		T35	1
all_values[2]	auto[1]	auto[1]	auto[1]	160	1			T21	5		T35	6		T36	4
all_values[3]	auto[0]	auto[0]	auto[0]	157	1			T21	4		T35	4		T172	1
all_values[3]	auto[0]	auto[0]	auto[1]	87	1			T21	2		T34	2		T35	1
all_values[3]	auto[0]	auto[1]	auto[0]	137	1			T21	1		T35	2		T172	2
all_values[3]	auto[0]	auto[1]	auto[1]	94	1			T21	1		T35	2		T36	2
all_values[3]	auto[1]	auto[0]	auto[1]	204	1			T21	7		T34	2		T35	6
all_values[3]	auto[1]	auto[1]	auto[1]	142	1			T21	5		T35	2		T36	1
all_values[4]	auto[0]	auto[0]	auto[0]	156	1			T21	5		T35	4		T36	2
all_values[4]	auto[0]	auto[0]	auto[1]	70	1			T21	1		T35	1		T174	1
all_values[4]	auto[0]	auto[1]	auto[0]	165	1			T21	3		T34	3		T35	5
all_values[4]	auto[0]	auto[1]	auto[1]	87	1			T21	3		T36	5		T172	1
all_values[4]	auto[1]	auto[0]	auto[1]	179	1			T21	4		T34	1		T35	4
all_values[4]	auto[1]	auto[1]	auto[1]	164	1			T21	4		T35	3		T36	3
all_values[5]	auto[0]	auto[0]	auto[0]	224	1			T21	5		T34	1		T35	6
all_values[5]	auto[0]	auto[1]	auto[0]	238	1			T21	10		T34	1		T35	4
all_values[5]	auto[1]	auto[0]	auto[1]	194	1			T21	3		T34	2		T35	3
all_values[5]	auto[1]	auto[1]	auto[1]	165	1			T21	2		T35	4		T36	3
all_values[6]	auto[0]	auto[0]	auto[0]	154	1			T21	4		T34	2		T35	3
all_values[6]	auto[0]	auto[0]	auto[1]	77	1			T21	1		T35	2		T36	3
all_values[6]	auto[0]	auto[1]	auto[0]	169	1			T21	2		T34	1		T35	1
all_values[6]	auto[0]	auto[1]	auto[1]	74	1			T21	5		T35	2		T36	1
all_values[6]	auto[1]	auto[0]	auto[1]	192	1			T21	5		T35	5		T36	1
all_values[6]	auto[1]	auto[1]	auto[1]	155	1			T21	3		T34	1		T35	4
all_values[7]	auto[0]	auto[0]	auto[0]	176	1			T21	4		T34	2		T35	2
all_values[7]	auto[0]	auto[0]	auto[1]	71	1			T21	4		T36	1		T173	2
all_values[7]	auto[0]	auto[1]	auto[0]	150	1			T21	2		T35	5		T36	3
all_values[7]	auto[0]	auto[1]	auto[1]	64	1			T35	1		T36	1		T172	1
all_values[7]	auto[1]	auto[0]	auto[1]	197	1			T21	4		T34	2		T35	3
all_values[7]	auto[1]	auto[1]	auto[1]	163	1			T21	6		T35	6		T36	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal