Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1801

1

T3

10

T4

4

T9

13

auto[1]

1787

1

T3

6

T4

1

T9

7

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2242

1

T9

20

T31

1

T44

8

auto[1]

1346

1

T3

16

T4

5

T25

4

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2734

1

T3

16

T4

5

T9

14

auto[1]

854

1

T9

6

T44

4

T47

4

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	697	1			T3	2		T4	2		T9	4
valid[1]	730	1			T3	2		T9	4		T25	2
valid[2]	722	1			T3	5		T4	1		T9	5
valid[3]	694	1			T3	3		T4	1		T9	5
valid[4]	745	1			T3	4		T4	1		T9	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	125	1			T9	1		T47	4		T45	1
auto[0]	auto[0]	valid[0]	auto[1]	127	1			T3	2		T4	1		T25	1
auto[0]	auto[0]	valid[1]	auto[0]	158	1			T9	3		T47	5		T49	1
auto[0]	auto[0]	valid[1]	auto[1]	125	1			T3	1		T27	5		T29	1
auto[0]	auto[0]	valid[2]	auto[0]	139	1			T9	2		T44	2		T45	1
auto[0]	auto[0]	valid[2]	auto[1]	139	1			T3	3		T4	1		T27	6
auto[0]	auto[0]	valid[3]	auto[0]	143	1			T9	3		T31	1		T47	1
auto[0]	auto[0]	valid[3]	auto[1]	121	1			T3	2		T4	1		T27	6
auto[0]	auto[0]	valid[4]	auto[0]	144	1			T9	1		T47	1		T46	1
auto[0]	auto[0]	valid[4]	auto[1]	142	1			T3	2		T4	1		T25	1
auto[0]	auto[1]	valid[0]	auto[0]	136	1			T9	1		T44	2		T47	1
auto[0]	auto[1]	valid[0]	auto[1]	133	1			T4	1		T27	3		T29	1
auto[0]	auto[1]	valid[1]	auto[0]	123	1			T9	1		T49	1		T46	1
auto[0]	auto[1]	valid[1]	auto[1]	146	1			T3	1		T25	2		T27	1
auto[0]	auto[1]	valid[2]	auto[0]	149	1			T9	1		T47	4		T343	1
auto[0]	auto[1]	valid[2]	auto[1]	138	1			T3	2		T27	2		T30	1
auto[0]	auto[1]	valid[3]	auto[0]	134	1			T9	1		T47	1		T46	1
auto[0]	auto[1]	valid[3]	auto[1]	141	1			T3	1		T27	5		T29	2
auto[0]	auto[1]	valid[4]	auto[0]	137	1			T47	2		T46	2		T343	2
auto[0]	auto[1]	valid[4]	auto[1]	134	1			T3	2		T27	1		T29	2
auto[1]	auto[0]	valid[0]	auto[0]	93	1			T9	1		T45	1		T46	1
auto[1]	auto[0]	valid[1]	auto[0]	88	1			T21	1		T46	1		T343	1
auto[1]	auto[0]	valid[2]	auto[0]	76	1			T9	1		T44	1		T49	1
auto[1]	auto[0]	valid[3]	auto[0]	82	1			T9	1		T44	1		T47	1
auto[1]	auto[0]	valid[4]	auto[0]	99	1			T47	2		T46	2		T33	1
auto[1]	auto[1]	valid[0]	auto[0]	83	1			T9	1		T33	1		T54	3
auto[1]	auto[1]	valid[1]	auto[0]	90	1			T46	1		T66	1		T54	1
auto[1]	auto[1]	valid[2]	auto[0]	81	1			T9	1		T47	1		T33	2
auto[1]	auto[1]	valid[3]	auto[0]	73	1			T44	2		T49	1		T34	2
auto[1]	auto[1]	valid[4]	auto[0]	89	1			T9	1		T46	2		T343	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal