Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

54842

1

T5

3

T9

481

T26

5

auto[1]

14427

1

T3

310

T4

5

T25

4

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49582

1

T3

310

T4

5

T5

1

auto[1]

19687

1

T5

2

T9

147

T26

2

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	35560	1			T3	155		T4	5		T5	3
others[1]	5777	1			T3	20		T9	43		T26	1
others[2]	5961	1			T3	27		T9	37		T27	39
others[3]	6731	1			T3	36		T9	47		T27	34
interest[1]	3802	1			T3	18		T9	29		T27	31
interest[4]	23194	1			T3	107		T4	5		T5	3
interest[64]	11438	1			T3	54		T9	73		T27	53

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	18014	1			T5	1		T9	172		T26	3
auto[0]	auto[0]	others[1]	2960	1			T9	34		T31	1		T44	17
auto[0]	auto[0]	others[2]	3030	1			T9	27		T31	1		T44	13
auto[0]	auto[0]	others[3]	3431	1			T9	36		T44	17		T47	34
auto[0]	auto[0]	interest[1]	1925	1			T9	17		T44	6		T47	13
auto[0]	auto[0]	interest[4]	11665	1			T5	1		T9	111		T31	1
auto[0]	auto[0]	interest[64]	5795	1			T9	48		T31	1		T44	26
auto[0]	auto[1]	others[0]	7557	1			T3	155		T4	5		T25	4
auto[0]	auto[1]	others[1]	1176	1			T3	20		T27	45		T29	12
auto[0]	auto[1]	others[2]	1218	1			T3	27		T27	39		T29	13
auto[0]	auto[1]	others[3]	1388	1			T3	36		T27	34		T29	18
auto[0]	auto[1]	interest[1]	796	1			T3	18		T27	31		T29	7
auto[0]	auto[1]	interest[4]	5080	1			T3	107		T4	5		T25	4
auto[0]	auto[1]	interest[64]	2292	1			T3	54		T27	53		T29	18
auto[1]	auto[0]	others[0]	9989	1			T5	2		T9	80		T26	1
auto[1]	auto[0]	others[1]	1641	1			T9	9		T26	1		T44	11
auto[1]	auto[0]	others[2]	1713	1			T9	10		T31	1		T44	10
auto[1]	auto[0]	others[3]	1912	1			T9	11		T31	1		T44	13
auto[1]	auto[0]	interest[1]	1081	1			T9	12		T31	1		T44	2
auto[1]	auto[0]	interest[4]	6449	1			T5	2		T9	55		T26	1
auto[1]	auto[0]	interest[64]	3351	1			T9	25		T44	21		T47	15

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal