Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3537414	1			T1	1		T2	1		T3	2
all_values[1]	3537414	1			T1	1		T2	1		T3	2
all_values[2]	3537414	1			T1	1		T2	1		T3	2
all_values[3]	3537414	1			T1	1		T2	1		T3	2
all_values[4]	3537414	1			T1	1		T2	1		T3	2
all_values[5]	3537414	1			T1	1		T2	1		T3	2
all_values[6]	3537414	1			T1	1		T2	1		T3	2
all_values[7]	3537414	1			T1	1		T2	1		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27281246

1

T1

8

T2

8

T3

16

auto[1]

1018066

1

T20

42

T23

45

T34

78342

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28267550

1

T1

8

T2

8

T3

16

auto[1]

31762

1

T29

4

T20

30

T50

100

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	3375518	1			T1	1		T2	1		T3	2
all_values[0]	auto[0]	auto[1]	14919	1			T29	4		T50	75		T23	2
all_values[0]	auto[1]	auto[0]	146323	1			T20	3		T23	2		T34	2
all_values[0]	auto[1]	auto[1]	654	1			T23	3		T34	4		T35	8
all_values[1]	auto[0]	auto[0]	3423628	1			T1	1		T2	1		T3	2
all_values[1]	auto[0]	auto[1]	9765	1			T20	1		T50	23		T23	3
all_values[1]	auto[1]	auto[0]	103566	1			T20	5		T23	4		T34	2
all_values[1]	auto[1]	auto[1]	455	1			T20	1		T23	1		T34	2
all_values[2]	auto[0]	auto[0]	3380779	1			T1	1		T2	1		T3	2
all_values[2]	auto[0]	auto[1]	3768	1			T20	1		T50	2		T23	2
all_values[2]	auto[1]	auto[0]	152530	1			T20	5		T23	6		T34	2
all_values[2]	auto[1]	auto[1]	337	1			T20	2		T23	3		T34	2
all_values[3]	auto[0]	auto[0]	3383422	1			T1	1		T2	1		T3	2
all_values[3]	auto[0]	auto[1]	215	1			T20	3		T23	1		T34	2
all_values[3]	auto[1]	auto[0]	153595	1			T20	3		T23	4		T34	26104
all_values[3]	auto[1]	auto[1]	182	1			T20	3		T23	5		T34	2
all_values[4]	auto[0]	auto[0]	3396056	1			T1	1		T2	1		T3	2
all_values[4]	auto[0]	auto[1]	197	1			T34	4		T35	1		T164	8
all_values[4]	auto[1]	auto[0]	140962	1			T20	1		T23	5		T34	3
all_values[4]	auto[1]	auto[1]	199	1			T20	2		T23	3		T34	3
all_values[5]	auto[0]	auto[0]	3382877	1			T1	1		T2	1		T3	2
all_values[5]	auto[0]	auto[1]	191	1			T20	3		T23	6		T35	4
all_values[5]	auto[1]	auto[0]	154178	1			T20	3		T23	2		T34	26105
all_values[5]	auto[1]	auto[1]	168	1			T20	3		T34	1		T35	3
all_values[6]	auto[0]	auto[0]	3513025	1			T1	1		T2	1		T3	2
all_values[6]	auto[0]	auto[1]	169	1			T20	3		T23	4		T34	2
all_values[6]	auto[1]	auto[0]	24052	1			T20	1		T23	2		T35	13
all_values[6]	auto[1]	auto[1]	168	1			T20	2		T23	1		T34	2
all_values[7]	auto[0]	auto[0]	3396523	1			T1	1		T2	1		T3	2
all_values[7]	auto[0]	auto[1]	194	1			T20	2		T23	4		T34	3
all_values[7]	auto[1]	auto[0]	140516	1			T20	4		T23	2		T34	26102
all_values[7]	auto[1]	auto[1]	181	1			T20	4		T23	2		T34	6