| Name |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.1610975044 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.940508228 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.4205544772 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.116213657 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.2881080743 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.2449461 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.1711627086 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.426964976 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1443243987 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.184797479 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.686685613 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3447381206 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3539180705 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1037074640 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.4119189143 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.983918046 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.2738920940 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.1971123572 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3164040283 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.3977619812 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.4287515038 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3990160709 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.319367796 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.1210148347 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2644972914 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.135231767 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1974197749 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.2277504558 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.439030868 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3524154590 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.356448110 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.3606438650 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.899104862 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.1267191400 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.3915628768 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1985425805 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.160114317 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.4266880514 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2917054483 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.980666871 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.877304259 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.660345883 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.801309556 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.3475655885 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2448583551 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_rw.1648494815 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_intr_test.3044420533 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3064755824 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_errors.3488639691 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.1839797958 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2873391400 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_rw.4129144035 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_intr_test.2772468448 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.778906474 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_errors.4219379317 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_intg_err.1446072332 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.978487757 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_rw.2086246498 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_intr_test.3178529972 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3821947297 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_errors.3809203921 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.2439238230 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1941476316 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_rw.3555369316 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_intr_test.2659267674 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1072317107 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_errors.1751813917 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2826657097 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_rw.3891641305 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_intr_test.1969099481 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3002249421 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_errors.3454419665 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.385646893 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3417997445 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_rw.451870621 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_intr_test.3713284592 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.756461627 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_errors.4012790903 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_aliasing.1191281986 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_bit_bash.651765065 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3130081406 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.2058091964 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.2148808121 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.1038249616 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.36306764 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3294447205 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.134428478 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/20.spi_device_intr_test.4250103306 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/21.spi_device_intr_test.1067640859 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/22.spi_device_intr_test.3474313077 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/23.spi_device_intr_test.1879425324 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/24.spi_device_intr_test.2226230672 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/25.spi_device_intr_test.3330741431 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/26.spi_device_intr_test.1868895410 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/27.spi_device_intr_test.119154640 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/28.spi_device_intr_test.3450601427 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/29.spi_device_intr_test.4154725199 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.71011116 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1400490906 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.231609458 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1358845872 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.523076793 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.2271533018 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.2199487497 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.1413412817 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2057496278 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.1200825866 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/30.spi_device_intr_test.1592271368 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/31.spi_device_intr_test.3420387551 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/32.spi_device_intr_test.2339633190 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/33.spi_device_intr_test.4284843193 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/34.spi_device_intr_test.2870445359 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/35.spi_device_intr_test.2832461808 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/36.spi_device_intr_test.1666198505 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/37.spi_device_intr_test.1894218643 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/38.spi_device_intr_test.3552177578 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/39.spi_device_intr_test.2491589161 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_aliasing.1436950572 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3214201517 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3955071276 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3687851268 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.3856892004 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.1434581634 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.2984059051 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.255732322 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.4174463753 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.4022461534 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.3208835263 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/40.spi_device_intr_test.2198523912 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/41.spi_device_intr_test.2819473992 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/42.spi_device_intr_test.2320170872 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/43.spi_device_intr_test.1195967026 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/44.spi_device_intr_test.2210883365 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/45.spi_device_intr_test.2720443643 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/46.spi_device_intr_test.1768973054 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/47.spi_device_intr_test.1514390148 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/48.spi_device_intr_test.911813497 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/49.spi_device_intr_test.838006697 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3059233323 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.771621305 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.3741092641 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2747610467 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.1958218593 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.4143067657 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.153372425 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_rw.1748750890 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.1741507914 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3650371214 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.1688685740 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.3932358164 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3130076117 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_rw.51952191 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_intr_test.186806429 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2044084481 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.3421106435 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.480884419 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2617403884 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_rw.793727641 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.1905926126 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2002203375 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.16212832 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.2883892680 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3372201290 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_rw.190807717 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_intr_test.2810723602 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2193178597 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.815854940 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_cfg_cmd.1073792020 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_all.699907230 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_intercept.3297248403 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_mailbox.2932040929 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.2972533767 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.2697956467 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.3817228244 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_all.2973815537 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_rw.1751354900 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.147139813 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_alert_test.132975281 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_cfg_cmd.1667648534 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_csb_read.482175405 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_all.664308456 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.800139112 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode.454900184 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.329918570 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_intercept.559955696 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.1477288911 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.3852621086 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.1055727073 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_sec_cm.4101550463 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_stress_all.2691622886 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.1443527041 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_rw.567147842 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.535961251 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_upload.2868439033 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_alert_test.1063782843 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_cfg_cmd.1094950234 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_csb_read.1591353695 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_all.1198841290 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode.1191407033 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.751287567 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_intercept.4072231169 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_mailbox.3258073884 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.1322075602 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.702121588 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.1639847713 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_stress_all.2696055774 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_all.1086466541 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.807650592 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_rw.2064756384 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.437680667 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_upload.740432059 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_alert_test.3965629401 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_cfg_cmd.660313678 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_csb_read.821805866 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_all.2137110781 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm.3366048152 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.1368135874 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode.1597916733 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_intercept.3292225924 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_mailbox.2983679166 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.4205571259 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.2664536187 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.1758727697 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_stress_all.1501644932 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_all.1258855952 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.1073666957 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_rw.3880784014 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.1157997390 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_upload.1847296272 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_alert_test.374179371 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_cfg_cmd.91943731 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_csb_read.3762403615 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_all.3718717975 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.3490111885 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.77311115 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode.1283666468 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode_ignore_cmds.1251783148 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_intercept.2922981297 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_mailbox.4029690548 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.3509359873 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.1643003327 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.735236079 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_stress_all.2390484720 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_all.642711317 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.1092237400 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_rw.111491392 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.3018370477 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_upload.110758895 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_alert_test.3436671637 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_cfg_cmd.1108826312 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_csb_read.1172360220 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_all.109470868 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm.4185987254 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm_min_idle.1791771029 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode.3928306850 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_intercept.529127684 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_mailbox.3765886055 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.3131122467 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_cmd_filtering.2283464656 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_read_buffer_direct.1366620763 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_stress_all.137318533 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_all.2460298354 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.759295700 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_rw.4062229528 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.2625436209 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_upload.1005112174 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_alert_test.2116542528 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_cfg_cmd.3302866621 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_csb_read.2723947845 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_all.964830165 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_and_tpm.2394985806 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_and_tpm_min_idle.329847954 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_mode.3037454811 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_mode_ignore_cmds.2950984756 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_intercept.3642982658 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_mailbox.756742825 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_pass_addr_payload_swap.443606333 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_pass_cmd_filtering.3990950349 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_read_buffer_direct.478554834 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_all.2356654472 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_read_hw_reg.2280948324 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_rw.2257741653 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_sts_read.370879102 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_upload.439732145 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_alert_test.1456553302 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_cfg_cmd.1030216746 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_csb_read.1660488056 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_all.2220874948 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_and_tpm.1274772362 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode.2400999769 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode_ignore_cmds.3671757611 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_intercept.620625206 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_mailbox.363112331 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_pass_addr_payload_swap.2475216225 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_pass_cmd_filtering.1175723459 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_read_buffer_direct.839183411 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_all.1446492213 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_read_hw_reg.3632132418 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_rw.1533288829 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_sts_read.3468129194 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_upload.2385760484 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_alert_test.103998750 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_cfg_cmd.3391059632 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_csb_read.3267783502 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_all.3109173612 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm.1931023318 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm_min_idle.2777575759 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_mode_ignore_cmds.4189943999 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_intercept.3626073202 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_mailbox.1003869095 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_pass_addr_payload_swap.803765805 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_pass_cmd_filtering.3377603627 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_read_buffer_direct.267520709 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_all.597356325 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_read_hw_reg.946675739 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_rw.2391629723 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_sts_read.3491283897 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_upload.4024086100 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_alert_test.1633742999 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_cfg_cmd.3072282146 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_csb_read.287047399 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_all.820562497 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_and_tpm.2229817248 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_and_tpm_min_idle.368166577 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_mode.2158972672 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_mode_ignore_cmds.4181274076 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_intercept.3876313197 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_mailbox.690276732 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_pass_addr_payload_swap.911550850 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_pass_cmd_filtering.1139987482 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_read_buffer_direct.4210588925 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_stress_all.1963068376 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_all.4028604371 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_read_hw_reg.3817545932 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_rw.2635682037 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_sts_read.773443514 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_upload.1705856512 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_alert_test.1093567244 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_cfg_cmd.701037506 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_csb_read.2821826381 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_all.1641061068 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm.1816511162 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm_min_idle.2956443598 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_mode.2555246928 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_mode_ignore_cmds.2961707667 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_intercept.330733698 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_mailbox.630757629 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_pass_addr_payload_swap.242619236 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_pass_cmd_filtering.2532619909 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_read_buffer_direct.3016751990 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_all.1243773029 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_read_hw_reg.3639671113 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_rw.2739822981 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_sts_read.4271685806 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_upload.1454613899 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_alert_test.1222229271 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_cfg_cmd.2643622553 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_csb_read.20519308 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm.3302745022 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_mode_ignore_cmds.1043272401 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_intercept.2701735233 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_mailbox.1723688741 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_pass_addr_payload_swap.747755199 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_pass_cmd_filtering.3886198272 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_read_buffer_direct.1015906456 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_stress_all.234012953 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_all.2389607325 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_read_hw_reg.2185240061 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_rw.3299142149 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_sts_read.3634059441 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_upload.2384761432 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_alert_test.1481629167 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_cfg_cmd.2954801621 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_csb_read.566185462 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_all.3438817330 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.4111642403 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode.3813878781 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_intercept.2311410459 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_mailbox.975472718 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.1929889824 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.398382887 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.3982825351 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_sec_cm.3774793652 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_all.3401646250 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.2545775858 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_rw.828453627 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.2941415682 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_upload.803860484 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_alert_test.1658734185 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_cfg_cmd.154209042 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_csb_read.4076399786 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_all.691948283 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_mode.2841807649 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_mode_ignore_cmds.3477922834 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_intercept.2213804786 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_mailbox.1537246553 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_pass_addr_payload_swap.2979974204 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_pass_cmd_filtering.168386939 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_read_buffer_direct.3810737326 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_stress_all.1516955713 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_all.2346829996 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_read_hw_reg.1682086308 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_rw.4190106285 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_sts_read.1838305227 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_upload.2028824677 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_alert_test.1316286841 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_cfg_cmd.2930868629 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_csb_read.626500637 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_all.127301337 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm.3177248469 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm_min_idle.1165287325 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_mode.2377112361 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_intercept.3928897363 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_mailbox.1101734432 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_pass_addr_payload_swap.314562207 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_pass_cmd_filtering.576929101 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_read_buffer_direct.2576774289 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_stress_all.398421677 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_all.956192874 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_read_hw_reg.2761881931 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_rw.4071152462 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_sts_read.265968958 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_upload.3220969133 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_alert_test.4239121156 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_cfg_cmd.322043480 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_csb_read.4007707320 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_all.803381414 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm.2437653025 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm_min_idle.3588175533 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_mode.4091188187 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_mode_ignore_cmds.1538580953 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_intercept.3433605267 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_mailbox.1242054362 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_pass_addr_payload_swap.1955097254 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_pass_cmd_filtering.1246562464 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_read_buffer_direct.2217111511 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_stress_all.213790777 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_all.1511322328 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_read_hw_reg.754359093 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_rw.730984634 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_sts_read.3170675862 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_upload.214993405 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_alert_test.2443242903 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_cfg_cmd.2715886835 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_csb_read.4138660117 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_all.335740647 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_and_tpm.6207813 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_mode.983564676 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_intercept.1870361565 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_mailbox.1170938976 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_pass_addr_payload_swap.2766382223 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_pass_cmd_filtering.1460791245 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_read_buffer_direct.2651298646 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_stress_all.768078075 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_all.3092497104 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_read_hw_reg.4076587446 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_rw.1173248696 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_sts_read.3416560420 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_upload.2471146752 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_alert_test.1425701084 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_cfg_cmd.3112331089 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_csb_read.3557211345 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_all.154666415 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_and_tpm.3881783197 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_and_tpm_min_idle.1986206588 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_mode.1988322695 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_mode_ignore_cmds.315634253 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_intercept.3925169779 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_mailbox.1514160887 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_pass_addr_payload_swap.4034687781 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_pass_cmd_filtering.3984155455 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_read_buffer_direct.40915161 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_stress_all.306902347 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_all.570030464 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_read_hw_reg.1733807962 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_rw.796523826 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_sts_read.1832063207 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_upload.422822260 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_alert_test.1859115626 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_cfg_cmd.834616350 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_csb_read.282974391 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_all.2718618445 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_and_tpm.3489986218 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_and_tpm_min_idle.3693606407 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_mode.4049494318 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_mode_ignore_cmds.2902390771 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_intercept.3389260908 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_mailbox.2558084349 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_pass_addr_payload_swap.3035950473 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_pass_cmd_filtering.2478525207 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_read_buffer_direct.2066081126 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_stress_all.2446675584 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_all.3705517550 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_read_hw_reg.1075384732 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_rw.593333494 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_sts_read.1088865377 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_upload.1756426901 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_alert_test.3535924010 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_cfg_cmd.891176243 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_csb_read.570132124 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_all.2098447843 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_and_tpm.4232450108 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_and_tpm_min_idle.76936048 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_mode.3362821005 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_mode_ignore_cmds.1108856201 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_intercept.2043722070 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_mailbox.335959536 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_pass_addr_payload_swap.2933255149 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_pass_cmd_filtering.4140280763 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_read_buffer_direct.2746906133 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_stress_all.698017683 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_all.1907048123 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_read_hw_reg.996664830 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_rw.766493175 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_sts_read.2583902367 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_upload.2876105464 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_alert_test.3432402831 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_cfg_cmd.2642646023 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_csb_read.422085291 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_all.3819734427 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_and_tpm.4093788327 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_and_tpm_min_idle.205576521 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_mode.2611548001 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_mode_ignore_cmds.3856758955 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_intercept.1112427580 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_mailbox.3088912699 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_pass_addr_payload_swap.1408368977 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_pass_cmd_filtering.90141525 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_read_buffer_direct.2830895022 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_stress_all.619323560 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_all.1883067446 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_read_hw_reg.646226659 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_rw.1225104 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_sts_read.4109744051 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_upload.4041076311 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_alert_test.845740673 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_cfg_cmd.1512109146 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_csb_read.2721108196 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_all.321921891 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm.2062872200 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm_min_idle.3700765472 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_mode.3104816785 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_mode_ignore_cmds.50314674 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_intercept.4110278270 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_mailbox.3660304565 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_pass_addr_payload_swap.3584247396 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_pass_cmd_filtering.1318700536 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_read_buffer_direct.1967425440 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_stress_all.3052611719 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_all.2803137881 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_read_hw_reg.1916371532 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_rw.4278348875 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_sts_read.1038374536 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_upload.1172154389 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_alert_test.575516642 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_cfg_cmd.3943239672 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_csb_read.344543307 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_all.3427640969 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_and_tpm.3280176070 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_and_tpm_min_idle.377991520 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_mode.3754235077 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_mode_ignore_cmds.1384186530 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_intercept.577298075 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_mailbox.2726578098 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_pass_addr_payload_swap.2136570741 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_pass_cmd_filtering.798129157 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_read_buffer_direct.3078743965 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_stress_all.3934220668 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_all.356957200 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_read_hw_reg.1093508015 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_rw.3632173942 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_sts_read.2520037449 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_upload.3171676842 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_alert_test.3967731585 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_cfg_cmd.2780364793 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_csb_read.4173559082 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.4093634998 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.163761749 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode.690497994 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.579708247 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_intercept.375596720 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_mailbox.2672579823 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.3909914131 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.4198937207 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_sec_cm.3112831832 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_stress_all.203279120 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_all.2996218068 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.2282847512 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_rw.3146441053 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.1289256529 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_upload.3527827202 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_alert_test.453885625 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_cfg_cmd.4271245298 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_csb_read.2285069859 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_all.1031212628 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_and_tpm.2479192660 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_and_tpm_min_idle.2735831649 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_mode_ignore_cmds.3270396391 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_intercept.727552371 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_mailbox.3227558727 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_pass_addr_payload_swap.3957042177 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_pass_cmd_filtering.3695639292 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_read_buffer_direct.3440903266 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_stress_all.189990873 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_all.2915139407 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_read_hw_reg.3083464518 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_rw.1003056558 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_sts_read.951986261 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_upload.1741812557 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_alert_test.1311541249 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_cfg_cmd.270799474 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_csb_read.1304131157 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_all.2681646694 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.1627643745 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.2052513108 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_mode.4242294547 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_mode_ignore_cmds.1622110888 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_intercept.851941928 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_mailbox.352930291 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_pass_addr_payload_swap.604233118 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_pass_cmd_filtering.4037866713 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_read_buffer_direct.1876643724 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_stress_all.3066611347 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_all.2548233233 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_read_hw_reg.4177853369 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_rw.1946197579 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_sts_read.804759880 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_upload.3861602648 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_alert_test.3025314998 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_cfg_cmd.4000973918 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_csb_read.1428837922 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_all.1387009016 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_and_tpm.855937163 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_and_tpm_min_idle.1615162744 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_mode.1298093666 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_mode_ignore_cmds.1766699226 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_intercept.3868434584 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_mailbox.3984197886 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_pass_addr_payload_swap.2213784138 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_pass_cmd_filtering.2805586862 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_read_buffer_direct.3906550669 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_stress_all.1335470967 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_all.3297882423 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_read_hw_reg.3471021250 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_rw.697218821 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_sts_read.3838282961 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_upload.463031914 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_alert_test.2670332324 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_cfg_cmd.3682276816 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_csb_read.583194496 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_all.4136877950 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_and_tpm.1249114335 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_and_tpm_min_idle.3093283857 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_mode.4245416942 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_mode_ignore_cmds.3548780639 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_intercept.37448143 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_mailbox.535013163 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_pass_addr_payload_swap.3074619547 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_pass_cmd_filtering.3547005652 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_read_buffer_direct.595191269 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_stress_all.635099757 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_all.2936013055 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_read_hw_reg.3253722177 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_rw.3634065714 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_sts_read.4030074938 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_upload.148405808 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_alert_test.2075317024 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_cfg_cmd.4209683710 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_csb_read.3001261097 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_all.2214391686 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm.194639054 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm_min_idle.3571217801 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_mode.151091221 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_mode_ignore_cmds.2609634172 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_intercept.3673647544 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_mailbox.4196128447 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_pass_addr_payload_swap.196649093 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_pass_cmd_filtering.4078151342 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_read_buffer_direct.549607413 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_stress_all.1422778482 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_all.1230480337 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_read_hw_reg.4084997756 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_rw.4053332418 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_sts_read.3159782675 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_upload.1908973545 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_alert_test.1325675794 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_cfg_cmd.1065484671 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_csb_read.4087921471 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_all.2113376963 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm.1824337355 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm_min_idle.3149828186 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_mode.1234161865 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_mode_ignore_cmds.3984386187 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_intercept.3594902699 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_mailbox.1431729543 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_pass_addr_payload_swap.565752802 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_pass_cmd_filtering.3318206605 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_read_buffer_direct.1683056280 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_stress_all.3488008982 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_all.1072631437 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_read_hw_reg.497793342 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_rw.1435662122 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_sts_read.3399629147 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_upload.2779547305 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_alert_test.3637763521 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_cfg_cmd.1694888362 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_csb_read.1023173978 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_all.2817432197 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.837877530 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.4130523514 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_mode.639713704 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_mode_ignore_cmds.1224535499 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_intercept.2004342829 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_mailbox.3330017654 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_pass_addr_payload_swap.4202256501 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_pass_cmd_filtering.3777284755 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_read_buffer_direct.3317156720 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_stress_all.4180875785 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_all.1698460267 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_read_hw_reg.2299784256 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_rw.1971131693 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_sts_read.2739922209 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_upload.1725724815 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_alert_test.2173992770 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_cfg_cmd.2968019641 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_csb_read.3286735560 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_all.529776410 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.1105897342 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.1768183227 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_mode.595330760 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_mode_ignore_cmds.3618204157 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_intercept.90997445 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_mailbox.1146716611 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_pass_addr_payload_swap.549490740 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_pass_cmd_filtering.3271014828 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_read_buffer_direct.1814224254 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_stress_all.1012039782 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_all.616383989 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_read_hw_reg.3790716258 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_rw.2766411264 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_sts_read.4042185358 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_upload.1752154853 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_alert_test.1931701216 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_cfg_cmd.396570017 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_csb_read.1490247663 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_all.2506460645 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.1222168008 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_mode.3105416035 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.4294232913 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_intercept.164241657 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_mailbox.3939315360 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_pass_addr_payload_swap.2887680039 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_pass_cmd_filtering.4058359900 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_read_buffer_direct.4095391326 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_stress_all.842367153 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_all.1247681478 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_read_hw_reg.4198689008 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_rw.1103610996 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_sts_read.2788617883 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_upload.846430993 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_alert_test.4038004841 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_cfg_cmd.316109248 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_csb_read.705943498 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_all.2987863313 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.1151611929 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.1357829799 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_mode.1752079625 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_mode_ignore_cmds.4121421647 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_intercept.2777539846 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_mailbox.974274903 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_pass_addr_payload_swap.2531488989 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_pass_cmd_filtering.1298242532 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_read_buffer_direct.2505993436 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_stress_all.3564968376 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_all.328300341 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_read_hw_reg.2706775680 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_rw.1340912328 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_sts_read.3741214886 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_upload.3227156529 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_alert_test.1768636379 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_cfg_cmd.4263188851 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_csb_read.160369824 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_all.3875459166 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.2622232505 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.2670564472 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode.2165626928 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.3098111820 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_intercept.1479019421 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_mailbox.325007754 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.2889171707 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.2229050598 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.944467144 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_sec_cm.3115021002 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_stress_all.3750383232 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.4245540675 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_rw.3225450723 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.198374596 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_upload.259067886 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_alert_test.3918628570 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_cfg_cmd.1781492369 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_csb_read.919204596 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_all.547314579 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.3585185815 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.119538416 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode.1260926555 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.3060441440 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_intercept.1838605746 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_mailbox.3118472597 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_pass_addr_payload_swap.972347334 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_pass_cmd_filtering.1562115823 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_read_buffer_direct.4093717957 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_stress_all.1360221140 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_all.2812720850 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_read_hw_reg.1238405310 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_rw.3590486083 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_sts_read.2272227031 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_upload.4112673056 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_alert_test.1820405268 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_cfg_cmd.3576297613 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_csb_read.2928728914 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_all.1857941002 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.2349086454 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.2543666218 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode.237917401 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.4217178042 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_intercept.433152173 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_mailbox.3052740394 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.867371933 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.1916731087 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.3924616754 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_stress_all.1148163744 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_all.1538597759 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_read_hw_reg.1077707418 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_rw.1955518434 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_sts_read.3420476442 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_upload.1045124579 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_alert_test.1196335004 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_cfg_cmd.1938682683 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_csb_read.2190606070 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_all.2722912990 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.2145072715 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.397355343 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode.906289885 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.3465047578 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_intercept.370447990 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_mailbox.1012763933 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.3615007176 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.2281520198 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.4164093106 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_stress_all.3074214501 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_all.612323735 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.2232513931 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_rw.3277112363 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.1026623181 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_upload.3946390040 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_alert_test.2807454572 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_cfg_cmd.2068292156 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_csb_read.1108039814 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_all.4281519178 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.2105093121 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.3096507849 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode.2407980236 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.2008123433 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_intercept.1993387594 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_mailbox.3171802330 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.4252161199 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.495130403 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.1419957844 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_stress_all.3486836931 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_all.3288776245 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.1678891658 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_rw.2331566050 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.92241092 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_upload.1521635596 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_alert_test.3311632434 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_cfg_cmd.582037621 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_csb_read.3895349866 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_all.1773925834 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.1752571917 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.1025943418 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode.2913739773 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.3153798708 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_intercept.2540877292 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_mailbox.2508115040 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.2793781151 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.1942917336 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.2142738575 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_stress_all.296134996 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_all.2505758030 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.2603774365 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_rw.262344582 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.921367483 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_upload.618196325 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_alert_test.276832860 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_cfg_cmd.1868971849 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_csb_read.4197387486 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_all.892431428 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.2304764523 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.765827390 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode.38011296 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.3961358079 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_intercept.2958895217 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_mailbox.2691317588 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.3695281536 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.3564220642 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.577746059 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_stress_all.2496082115 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_all.3518591770 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.1496083642 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_rw.2436854249 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.3827290916 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_upload.465313734 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_alert_test.3121165843 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_cfg_cmd.2099645203 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_csb_read.3333142088 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_all.2093508562 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.2946441016 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.770244702 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode.499452785 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.1520100667 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_intercept.1503455386 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_mailbox.2344520234 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.3483809435 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.3721253407 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.4211340276 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_stress_all.1747438511 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_all.957207338 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.1489210833 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_rw.1460518031 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.3892969511 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_upload.990807825 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_alert_test.2534369871 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_cfg_cmd.3958645138 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_csb_read.2116796687 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_all.3069558279 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.1032100530 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.728419708 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode.760600428 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.1801167377 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_intercept.2842089218 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_mailbox.2083386336 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.1162233385 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.510284842 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.709513982 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_stress_all.1434394750 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_all.2989859915 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.2680880898 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_rw.46736932 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.2041425993 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_upload.3473842382 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_alert_test.2580748648 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_cfg_cmd.916601751 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_csb_read.1317397844 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_all.1627617758 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.922913777 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.2920888562 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode.3824548279 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.75472750 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_intercept.1590577732 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_mailbox.858071256 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.3711902067 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.2642168263 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.1034385363 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_stress_all.1822705876 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_all.3982044608 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.2838325478 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_rw.113401524 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.3730266857 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_upload.3296435384 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_alert_test.1350812314 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_cfg_cmd.3249142160 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_csb_read.2696176050 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_all.727360447 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.2070644155 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.2167152290 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode.578521163 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.549481000 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_intercept.3084823756 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_mailbox.3179943029 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.2923684638 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.877509285 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.2102983319 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_stress_all.647254094 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_all.3280966925 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.1079243466 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_rw.144285180 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.3604437050 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_upload.1364465683 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_alert_test.2337827569 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_cfg_cmd.3812580700 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_csb_read.3396731847 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_all.709928192 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.2457450374 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.2759612634 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode.2931157454 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_intercept.1812073758 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_mailbox.1923020545 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.653148827 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.597382596 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.4013556370 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_all.1955124328 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.819681575 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_rw.3907815031 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.159819618 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_upload.3724817046 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_alert_test.1023600975 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_cfg_cmd.470037041 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_csb_read.283965174 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_all.711755482 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.2804502330 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.929324533 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode.1255407569 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.380904213 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_intercept.1421611576 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_mailbox.229370174 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.3915254042 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.1327707765 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.2166114490 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_stress_all.2543571966 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_all.2774381145 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.966902111 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_rw.3367736628 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.848342266 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_upload.2158065303 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_alert_test.777055106 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_cfg_cmd.567331936 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_csb_read.3491619952 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_all.3275899884 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.2310210770 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.1344199796 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode.2689872985 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_intercept.3914381769 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_mailbox.1391528855 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.1952106500 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.845741586 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.2671225789 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_stress_all.128309149 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_all.854505049 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.1749069885 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_rw.1671957826 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.3048985226 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_upload.1851378262 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_alert_test.238353716 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_cfg_cmd.4016982997 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_csb_read.642995604 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_all.1093314419 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode.112772861 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.2711902525 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_intercept.2923900864 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_mailbox.3536427278 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.2533860978 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.1004769736 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.1510320 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_stress_all.2350242834 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_all.2114944806 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.1463878699 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_rw.356924082 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.3150064170 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_upload.1826510975 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_alert_test.618664106 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_cfg_cmd.840276229 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_csb_read.2484985805 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_all.56135359 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.1946888232 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode.2622777245 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.640087448 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_intercept.1384019397 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_mailbox.3807399154 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.967891564 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.4256080121 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.827384519 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_all.733577780 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.900469564 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_rw.2996674860 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.2429281648 |
| /workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_upload.190220718 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_csb_read.2389488078 |
|
|
Sep 18 02:21:38 PM UTC 24 |
Sep 18 02:21:40 PM UTC 24 |
14551056 ps |
| T2 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_ram_cfg.536495254 |
|
|
Sep 18 02:21:44 PM UTC 24 |
Sep 18 02:21:46 PM UTC 24 |
17810688 ps |
| T3 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_all.2973815537 |
|
|
Sep 18 02:21:46 PM UTC 24 |
Sep 18 02:21:48 PM UTC 24 |
20465918 ps |
| T4 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.147139813 |
|
|
Sep 18 02:21:48 PM UTC 24 |
Sep 18 02:21:50 PM UTC 24 |
34770915 ps |
| T5 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_rw.1751354900 |
|
|
Sep 18 02:21:49 PM UTC 24 |
Sep 18 02:21:52 PM UTC 24 |
59110805 ps |
| T6 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.2697956467 |
|
|
Sep 18 02:21:51 PM UTC 24 |
Sep 18 02:21:57 PM UTC 24 |
211988405 ps |
| T7 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.3996354441 |
|
|
Sep 18 02:21:44 PM UTC 24 |
Sep 18 02:21:58 PM UTC 24 |
2326997995 ps |
| T8 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_mailbox.2932040929 |
|
|
Sep 18 02:21:59 PM UTC 24 |
Sep 18 02:22:15 PM UTC 24 |
796513925 ps |
| T9 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_intercept.3297248403 |
|
|
Sep 18 02:21:58 PM UTC 24 |
Sep 18 02:22:25 PM UTC 24 |
6685132858 ps |
| T10 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_upload.2081232392 |
|
|
Sep 18 02:22:16 PM UTC 24 |
Sep 18 02:22:28 PM UTC 24 |
4071535632 ps |
| T24 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_cfg_cmd.1073792020 |
|
|
Sep 18 02:22:25 PM UTC 24 |
Sep 18 02:22:29 PM UTC 24 |
46859102 ps |
| T11 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.3817228244 |
|
|
Sep 18 02:22:31 PM UTC 24 |
Sep 18 02:22:43 PM UTC 24 |
438687524 ps |
| T12 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.2972533767 |
|
|
Sep 18 02:21:53 PM UTC 24 |
Sep 18 02:22:45 PM UTC 24 |
18595055962 ps |
| T13 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode.4043018003 |
|
|
Sep 18 02:22:26 PM UTC 24 |
Sep 18 02:22:57 PM UTC 24 |
2388306878 ps |
| T14 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_sec_cm.2440792963 |
|
|
Sep 18 02:22:58 PM UTC 24 |
Sep 18 02:23:01 PM UTC 24 |
82115952 ps |
| T25 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_alert_test.4034500093 |
|
|
Sep 18 02:23:02 PM UTC 24 |
Sep 18 02:23:04 PM UTC 24 |
19897847 ps |
| T15 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_csb_read.482175405 |
|
|
Sep 18 02:23:05 PM UTC 24 |
Sep 18 02:23:08 PM UTC 24 |
20189803 ps |
| T16 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_all.699907230 |
|
|
Sep 18 02:22:33 PM UTC 24 |
Sep 18 02:23:15 PM UTC 24 |
6273444070 ps |
| T26 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.535961251 |
|
|
Sep 18 02:23:16 PM UTC 24 |
Sep 18 02:23:18 PM UTC 24 |
121971115 ps |
| T27 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_rw.567147842 |
|
|
Sep 18 02:23:19 PM UTC 24 |
Sep 18 02:23:21 PM UTC 24 |
32469234 ps |
| T28 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.1443527041 |
|
|
Sep 18 02:23:10 PM UTC 24 |
Sep 18 02:23:34 PM UTC 24 |
6914336469 ps |
| T17 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_intercept.559955696 |
|
|
Sep 18 02:23:26 PM UTC 24 |
Sep 18 02:23:34 PM UTC 24 |
478520838 ps |
| T18 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.1477288911 |
|
|
Sep 18 02:23:22 PM UTC 24 |
Sep 18 02:23:38 PM UTC 24 |
5718249057 ps |
| T37 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_cfg_cmd.1667648534 |
|
|
Sep 18 02:23:39 PM UTC 24 |
Sep 18 02:23:47 PM UTC 24 |
118769920 ps |
| T41 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_upload.2868439033 |
|
|
Sep 18 02:23:36 PM UTC 24 |
Sep 18 02:23:54 PM UTC 24 |
975887810 ps |
| T38 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode.454900184 |
|
|
Sep 18 02:23:48 PM UTC 24 |
Sep 18 02:24:04 PM UTC 24 |
765222415 ps |
| T29 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.459516840 |
|
|
Sep 18 02:22:44 PM UTC 24 |
Sep 18 02:24:09 PM UTC 24 |
33811612016 ps |
| T55 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.3852621086 |
|
|
Sep 18 02:23:22 PM UTC 24 |
Sep 18 02:24:12 PM UTC 24 |
19525605571 ps |
| T19 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_sec_cm.4101550463 |
|
|
Sep 18 02:24:14 PM UTC 24 |
Sep 18 02:24:16 PM UTC 24 |
273171017 ps |
| T20 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_stress_all.2691622886 |
|
|
Sep 18 02:24:12 PM UTC 24 |
Sep 18 02:24:16 PM UTC 24 |
72856296 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_alert_test.132975281 |
|
|
Sep 18 02:24:17 PM UTC 24 |
Sep 18 02:24:19 PM UTC 24 |
13466402 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_csb_read.566185462 |
|
|
Sep 18 02:24:17 PM UTC 24 |
Sep 18 02:24:19 PM UTC 24 |
23042649 ps |
| T30 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.2545775858 |
|
|
Sep 18 02:24:20 PM UTC 24 |
Sep 18 02:24:23 PM UTC 24 |
396905837 ps |
| T31 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_all.3243187571 |
|
|
Sep 18 02:23:12 PM UTC 24 |
Sep 18 02:24:25 PM UTC 24 |
8866256826 ps |
| T32 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.2941415682 |
|
|
Sep 18 02:24:24 PM UTC 24 |
Sep 18 02:24:26 PM UTC 24 |
49661900 ps |
| T53 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.1055727073 |
|
|
Sep 18 02:24:05 PM UTC 24 |
Sep 18 02:24:26 PM UTC 24 |
1584526359 ps |
| T44 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_rw.828453627 |
|
|
Sep 18 02:24:26 PM UTC 24 |
Sep 18 02:24:29 PM UTC 24 |
40293891 ps |
| T56 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.398382887 |
|
|
Sep 18 02:24:27 PM UTC 24 |
Sep 18 02:24:40 PM UTC 24 |
15832976702 ps |
| T45 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.1926036298 |
|
|
Sep 18 02:22:28 PM UTC 24 |
Sep 18 02:24:43 PM UTC 24 |
34993066342 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_intercept.2311410459 |
|
|
Sep 18 02:24:30 PM UTC 24 |
Sep 18 02:24:46 PM UTC 24 |
10711263070 ps |
| T95 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_cfg_cmd.2954801621 |
|
|
Sep 18 02:24:44 PM UTC 24 |
Sep 18 02:24:51 PM UTC 24 |
872698017 ps |
| T54 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_upload.803860484 |
|
|
Sep 18 02:24:42 PM UTC 24 |
Sep 18 02:24:53 PM UTC 24 |
46045918494 ps |
| T42 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_all.3401646250 |
|
|
Sep 18 02:24:23 PM UTC 24 |
Sep 18 02:24:59 PM UTC 24 |
2082570087 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode.3813878781 |
|
|
Sep 18 02:24:47 PM UTC 24 |
Sep 18 02:25:00 PM UTC 24 |
198569832 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_all.3438817330 |
|
|
Sep 18 02:24:59 PM UTC 24 |
Sep 18 02:25:02 PM UTC 24 |
71603475 ps |
| T183 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.1929889824 |
|
|
Sep 18 02:24:27 PM UTC 24 |
Sep 18 02:25:07 PM UTC 24 |
9333974302 ps |
| T153 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.3982825351 |
|
|
Sep 18 02:24:54 PM UTC 24 |
Sep 18 02:25:14 PM UTC 24 |
1680460320 ps |
| T96 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_mailbox.975472718 |
|
|
Sep 18 02:24:36 PM UTC 24 |
Sep 18 02:25:16 PM UTC 24 |
2822118805 ps |
| T21 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_sec_cm.3774793652 |
|
|
Sep 18 02:25:15 PM UTC 24 |
Sep 18 02:25:19 PM UTC 24 |
86911445 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_alert_test.1481629167 |
|
|
Sep 18 02:25:18 PM UTC 24 |
Sep 18 02:25:20 PM UTC 24 |
14118899 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_csb_read.4173559082 |
|
|
Sep 18 02:25:18 PM UTC 24 |
Sep 18 02:25:20 PM UTC 24 |
18768185 ps |
| T92 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.1289256529 |
|
|
Sep 18 02:25:22 PM UTC 24 |
Sep 18 02:25:25 PM UTC 24 |
355021819 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_mailbox.947379715 |
|
|
Sep 18 02:23:34 PM UTC 24 |
Sep 18 02:25:26 PM UTC 24 |
8595348811 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_rw.3146441053 |
|
|
Sep 18 02:25:24 PM UTC 24 |
Sep 18 02:25:27 PM UTC 24 |
12098882 ps |
| T93 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.2282847512 |
|
|
Sep 18 02:25:20 PM UTC 24 |
Sep 18 02:25:28 PM UTC 24 |
1517919154 ps |
| T46 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.2008094092 |
|
|
Sep 18 02:25:01 PM UTC 24 |
Sep 18 02:25:29 PM UTC 24 |
15582410207 ps |
| T57 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_intercept.375596720 |
|
|
Sep 18 02:25:27 PM UTC 24 |
Sep 18 02:25:35 PM UTC 24 |
114611488 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_cfg_cmd.2780364793 |
|
|
Sep 18 02:25:31 PM UTC 24 |
Sep 18 02:25:35 PM UTC 24 |
30293643 ps |
| T58 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_all.664308456 |
|
|
Sep 18 02:24:07 PM UTC 24 |
Sep 18 02:25:35 PM UTC 24 |
17740157959 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_mailbox.2672579823 |
|
|
Sep 18 02:25:28 PM UTC 24 |
Sep 18 02:25:37 PM UTC 24 |
245627756 ps |
| T61 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.3909914131 |
|
|
Sep 18 02:25:27 PM UTC 24 |
Sep 18 02:25:41 PM UTC 24 |
3397424721 ps |
| T52 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode.690497994 |
|
|
Sep 18 02:25:36 PM UTC 24 |
Sep 18 02:25:43 PM UTC 24 |
53164012 ps |
| T154 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.4198937207 |
|
|
Sep 18 02:25:36 PM UTC 24 |
Sep 18 02:25:43 PM UTC 24 |
381489073 ps |
| T65 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_all.2996218068 |
|
|
Sep 18 02:25:22 PM UTC 24 |
Sep 18 02:25:46 PM UTC 24 |
14555440103 ps |
| T100 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_upload.3527827202 |
|
|
Sep 18 02:25:30 PM UTC 24 |
Sep 18 02:25:48 PM UTC 24 |
32356934982 ps |
| T22 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_sec_cm.3112831832 |
|
|
Sep 18 02:25:46 PM UTC 24 |
Sep 18 02:25:49 PM UTC 24 |
54857241 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_alert_test.3967731585 |
|
|
Sep 18 02:25:49 PM UTC 24 |
Sep 18 02:25:52 PM UTC 24 |
23709489 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_csb_read.160369824 |
|
|
Sep 18 02:25:50 PM UTC 24 |
Sep 18 02:25:52 PM UTC 24 |
63732592 ps |
| T223 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.2915149294 |
|
|
Sep 18 02:25:26 PM UTC 24 |
Sep 18 02:25:53 PM UTC 24 |
10005245254 ps |
| T94 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.198374596 |
|
|
Sep 18 02:25:54 PM UTC 24 |
Sep 18 02:25:56 PM UTC 24 |
35341383 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.4245540675 |
|
|
Sep 18 02:25:53 PM UTC 24 |
Sep 18 02:25:57 PM UTC 24 |
1140549612 ps |
| T66 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_rw.3225450723 |
|
|
Sep 18 02:25:56 PM UTC 24 |
Sep 18 02:26:02 PM UTC 24 |
63002068 ps |
| T244 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_intercept.1479019421 |
|
|
Sep 18 02:25:58 PM UTC 24 |
Sep 18 02:26:05 PM UTC 24 |
275086936 ps |
| T59 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.2229050598 |
|
|
Sep 18 02:25:57 PM UTC 24 |
Sep 18 02:26:07 PM UTC 24 |
885157971 ps |
| T43 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_all.2841250817 |
|
|
Sep 18 02:25:53 PM UTC 24 |
Sep 18 02:26:08 PM UTC 24 |
7181647878 ps |
| T188 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_upload.259067886 |
|
|
Sep 18 02:26:06 PM UTC 24 |
Sep 18 02:26:11 PM UTC 24 |
1179186400 ps |
| T203 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_cfg_cmd.4263188851 |
|
|
Sep 18 02:26:09 PM UTC 24 |
Sep 18 02:26:13 PM UTC 24 |
79316638 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.3098111820 |
|
|
Sep 18 02:26:12 PM UTC 24 |
Sep 18 02:26:14 PM UTC 24 |
40501079 ps |
| T155 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.944467144 |
|
|
Sep 18 02:26:14 PM UTC 24 |
Sep 18 02:26:25 PM UTC 24 |
501565717 ps |
| T207 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.2889171707 |
|
|
Sep 18 02:25:58 PM UTC 24 |
Sep 18 02:26:28 PM UTC 24 |
15278650429 ps |
| T50 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.1661128059 |
|
|
Sep 18 02:24:10 PM UTC 24 |
Sep 18 02:26:30 PM UTC 24 |
38540576750 ps |
| T23 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_stress_all.3750383232 |
|
|
Sep 18 02:26:28 PM UTC 24 |
Sep 18 02:26:31 PM UTC 24 |
61367824 ps |
| T33 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_sec_cm.3115021002 |
|
|
Sep 18 02:26:30 PM UTC 24 |
Sep 18 02:26:33 PM UTC 24 |
374043870 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_alert_test.1768636379 |
|
|
Sep 18 02:26:32 PM UTC 24 |
Sep 18 02:26:34 PM UTC 24 |
31553195 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_csb_read.3396731847 |
|
|
Sep 18 02:26:34 PM UTC 24 |
Sep 18 02:26:36 PM UTC 24 |
62982896 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.2429281648 |
|
|
Sep 18 02:29:15 PM UTC 24 |
Sep 18 02:29:17 PM UTC 24 |
15732030 ps |
| T62 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.579708247 |
|
|
Sep 18 02:25:36 PM UTC 24 |
Sep 18 02:26:37 PM UTC 24 |
3656143279 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.159819618 |
|
|
Sep 18 02:26:38 PM UTC 24 |
Sep 18 02:26:40 PM UTC 24 |
35355953 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_all.1955124328 |
|
|
Sep 18 02:26:38 PM UTC 24 |
Sep 18 02:26:43 PM UTC 24 |
491127004 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_rw.3907815031 |
|
|
Sep 18 02:26:41 PM UTC 24 |
Sep 18 02:26:44 PM UTC 24 |
229336288 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode.2165626928 |
|
|
Sep 18 02:26:10 PM UTC 24 |
Sep 18 02:26:48 PM UTC 24 |
6216354869 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.819681575 |
|
|
Sep 18 02:26:37 PM UTC 24 |
Sep 18 02:26:50 PM UTC 24 |
5644292025 ps |
| T263 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_intercept.1812073758 |
|
|
Sep 18 02:26:45 PM UTC 24 |
Sep 18 02:26:52 PM UTC 24 |
115683284 ps |
| T51 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.4093634998 |
|
|
Sep 18 02:25:42 PM UTC 24 |
Sep 18 02:26:54 PM UTC 24 |
2315768597 ps |
| T184 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.597382596 |
|
|
Sep 18 02:26:44 PM UTC 24 |
Sep 18 02:26:54 PM UTC 24 |
1049865013 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_upload.3724817046 |
|
|
Sep 18 02:26:50 PM UTC 24 |
Sep 18 02:26:55 PM UTC 24 |
103720106 ps |
| T63 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.653148827 |
|
|
Sep 18 02:26:44 PM UTC 24 |
Sep 18 02:26:57 PM UTC 24 |
436715528 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_mailbox.325007754 |
|
|
Sep 18 02:26:02 PM UTC 24 |
Sep 18 02:26:58 PM UTC 24 |
19548535047 ps |
| T190 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode.2931157454 |
|
|
Sep 18 02:26:55 PM UTC 24 |
Sep 18 02:27:09 PM UTC 24 |
843643949 ps |
| T156 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.4013556370 |
|
|
Sep 18 02:26:56 PM UTC 24 |
Sep 18 02:27:10 PM UTC 24 |
701582284 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_alert_test.2337827569 |
|
|
Sep 18 02:27:11 PM UTC 24 |
Sep 18 02:27:14 PM UTC 24 |
12238364 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_csb_read.283965174 |
|
|
Sep 18 02:27:15 PM UTC 24 |
Sep 18 02:27:17 PM UTC 24 |
20695213 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_all.3875459166 |
|
|
Sep 18 02:26:15 PM UTC 24 |
Sep 18 02:27:20 PM UTC 24 |
1985570078 ps |
| T265 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_cfg_cmd.3812580700 |
|
|
Sep 18 02:26:54 PM UTC 24 |
Sep 18 02:27:21 PM UTC 24 |
2688895620 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.848342266 |
|
|
Sep 18 02:27:20 PM UTC 24 |
Sep 18 02:27:23 PM UTC 24 |
92993347 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.966902111 |
|
|
Sep 18 02:27:18 PM UTC 24 |
Sep 18 02:27:28 PM UTC 24 |
4883380131 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.1327707765 |
|
|
Sep 18 02:27:23 PM UTC 24 |
Sep 18 02:27:28 PM UTC 24 |
152150068 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_rw.3367736628 |
|
|
Sep 18 02:27:22 PM UTC 24 |
Sep 18 02:27:30 PM UTC 24 |
127722852 ps |
| T97 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_mailbox.1923020545 |
|
|
Sep 18 02:26:49 PM UTC 24 |
Sep 18 02:27:33 PM UTC 24 |
3513113845 ps |
| T262 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_mailbox.229370174 |
|
|
Sep 18 02:27:31 PM UTC 24 |
Sep 18 02:27:37 PM UTC 24 |
609129944 ps |
| T189 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_upload.2158065303 |
|
|
Sep 18 02:27:33 PM UTC 24 |
Sep 18 02:27:43 PM UTC 24 |
6524003563 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_cfg_cmd.470037041 |
|
|
Sep 18 02:27:37 PM UTC 24 |
Sep 18 02:27:55 PM UTC 24 |
5239665669 ps |
| T60 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.1377033895 |
|
|
Sep 18 02:26:55 PM UTC 24 |
Sep 18 02:27:56 PM UTC 24 |
2865171908 ps |
| T245 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_intercept.1421611576 |
|
|
Sep 18 02:27:28 PM UTC 24 |
Sep 18 02:27:57 PM UTC 24 |
9117814154 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_all.2774381145 |
|
|
Sep 18 02:27:19 PM UTC 24 |
Sep 18 02:27:57 PM UTC 24 |
17125794156 ps |
| T157 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.2166114490 |
|
|
Sep 18 02:27:57 PM UTC 24 |
Sep 18 02:28:04 PM UTC 24 |
706523652 ps |
| T64 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.163761749 |
|
|
Sep 18 02:25:43 PM UTC 24 |
Sep 18 02:28:20 PM UTC 24 |
29200579121 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_alert_test.1023600975 |
|
|
Sep 18 02:28:20 PM UTC 24 |
Sep 18 02:28:22 PM UTC 24 |
15616694 ps |
| T242 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode.1255407569 |
|
|
Sep 18 02:27:44 PM UTC 24 |
Sep 18 02:28:23 PM UTC 24 |
1788252381 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_csb_read.3491619952 |
|
|
Sep 18 02:28:23 PM UTC 24 |
Sep 18 02:28:26 PM UTC 24 |
41598313 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_csb_read.2484985805 |
|
|
Sep 18 02:29:11 PM UTC 24 |
Sep 18 02:29:13 PM UTC 24 |
53844665 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.1749069885 |
|
|
Sep 18 02:28:25 PM UTC 24 |
Sep 18 02:28:27 PM UTC 24 |
12990624 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.3048985226 |
|
|
Sep 18 02:28:27 PM UTC 24 |
Sep 18 02:28:29 PM UTC 24 |
130523644 ps |
| T291 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.3915254042 |
|
|
Sep 18 02:27:28 PM UTC 24 |
Sep 18 02:28:30 PM UTC 24 |
42198752636 ps |
| T34 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_stress_all.2074328860 |
|
|
Sep 18 02:22:46 PM UTC 24 |
Sep 18 02:28:31 PM UTC 24 |
197363115634 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.329918570 |
|
|
Sep 18 02:23:55 PM UTC 24 |
Sep 18 02:28:32 PM UTC 24 |
124430273743 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_rw.1671957826 |
|
|
Sep 18 02:28:28 PM UTC 24 |
Sep 18 02:28:32 PM UTC 24 |
371552405 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_all.854505049 |
|
|
Sep 18 02:28:25 PM UTC 24 |
Sep 18 02:28:33 PM UTC 24 |
806615709 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.1952106500 |
|
|
Sep 18 02:28:30 PM UTC 24 |
Sep 18 02:28:34 PM UTC 24 |
60614986 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_intercept.3914381769 |
|
|
Sep 18 02:28:31 PM UTC 24 |
Sep 18 02:28:35 PM UTC 24 |
57938126 ps |
| T98 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_cfg_cmd.567331936 |
|
|
Sep 18 02:28:32 PM UTC 24 |
Sep 18 02:28:36 PM UTC 24 |
190493351 ps |
| T273 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.845741586 |
|
|
Sep 18 02:28:28 PM UTC 24 |
Sep 18 02:28:36 PM UTC 24 |
1042286513 ps |
| T271 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_upload.1851378262 |
|
|
Sep 18 02:28:32 PM UTC 24 |
Sep 18 02:28:36 PM UTC 24 |
84852384 ps |
| T47 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.2043323862 |
|
|
Sep 18 02:22:44 PM UTC 24 |
Sep 18 02:28:41 PM UTC 24 |
54083780200 ps |
| T35 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_stress_all.128309149 |
|
|
Sep 18 02:28:42 PM UTC 24 |
Sep 18 02:28:45 PM UTC 24 |
47034835 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_alert_test.777055106 |
|
|
Sep 18 02:28:45 PM UTC 24 |
Sep 18 02:28:47 PM UTC 24 |
11164550 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.2671225789 |
|
|
Sep 18 02:28:37 PM UTC 24 |
Sep 18 02:28:47 PM UTC 24 |
3574090584 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_rw.2996674860 |
|
|
Sep 18 02:29:16 PM UTC 24 |
Sep 18 02:29:19 PM UTC 24 |
94229726 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_csb_read.642995604 |
|
|
Sep 18 02:28:48 PM UTC 24 |
Sep 18 02:28:50 PM UTC 24 |
45216921 ps |
| T185 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_all.2637251288 |
|
|
Sep 18 02:25:38 PM UTC 24 |
Sep 18 02:28:51 PM UTC 24 |
16529342460 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_all.2114944806 |
|
|
Sep 18 02:28:51 PM UTC 24 |
Sep 18 02:28:53 PM UTC 24 |
27432353 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.3150064170 |
|
|
Sep 18 02:28:52 PM UTC 24 |
Sep 18 02:28:55 PM UTC 24 |
94379217 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.380904213 |
|
|
Sep 18 02:27:56 PM UTC 24 |
Sep 18 02:28:55 PM UTC 24 |
2503915010 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_rw.356924082 |
|
|
Sep 18 02:28:54 PM UTC 24 |
Sep 18 02:28:58 PM UTC 24 |
814297214 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_mailbox.3536427278 |
|
|
Sep 18 02:28:56 PM UTC 24 |
Sep 18 02:29:00 PM UTC 24 |
60973635 ps |
| T264 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_mailbox.1391528855 |
|
|
Sep 18 02:28:32 PM UTC 24 |
Sep 18 02:29:02 PM UTC 24 |
4054158605 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_intercept.2923900864 |
|
|
Sep 18 02:28:55 PM UTC 24 |
Sep 18 02:29:02 PM UTC 24 |
1844438978 ps |
| T255 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_cfg_cmd.4016982997 |
|
|
Sep 18 02:28:58 PM UTC 24 |
Sep 18 02:29:02 PM UTC 24 |
232005383 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode.2689872985 |
|
|
Sep 18 02:28:33 PM UTC 24 |
Sep 18 02:29:03 PM UTC 24 |
1624750088 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.1004769736 |
|
|
Sep 18 02:28:54 PM UTC 24 |
Sep 18 02:29:05 PM UTC 24 |
5180981582 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.1463878699 |
|
|
Sep 18 02:28:51 PM UTC 24 |
Sep 18 02:29:05 PM UTC 24 |
1203758927 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.2533860978 |
|
|
Sep 18 02:28:54 PM UTC 24 |
Sep 18 02:29:08 PM UTC 24 |
1683734989 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode.112772861 |
|
|
Sep 18 02:29:01 PM UTC 24 |
Sep 18 02:29:11 PM UTC 24 |
501705067 ps |
| T206 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_upload.1826510975 |
|
|
Sep 18 02:28:57 PM UTC 24 |
Sep 18 02:29:11 PM UTC 24 |
5598988182 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_alert_test.238353716 |
|
|
Sep 18 02:29:09 PM UTC 24 |
Sep 18 02:29:11 PM UTC 24 |
31959426 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.1510320 |
|
|
Sep 18 02:29:03 PM UTC 24 |
Sep 18 02:29:12 PM UTC 24 |
597872261 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.900469564 |
|
|
Sep 18 02:29:12 PM UTC 24 |
Sep 18 02:29:18 PM UTC 24 |
446049597 ps |
| T222 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.4256080121 |
|
|
Sep 18 02:29:18 PM UTC 24 |
Sep 18 02:29:29 PM UTC 24 |
376954799 ps |
| T286 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.967891564 |
|
|
Sep 18 02:29:19 PM UTC 24 |
Sep 18 02:29:31 PM UTC 24 |
565536635 ps |
| T221 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_mailbox.3807399154 |
|
|
Sep 18 02:29:29 PM UTC 24 |
Sep 18 02:29:45 PM UTC 24 |
406644472 ps |
| T248 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_intercept.1384019397 |
|
|
Sep 18 02:29:19 PM UTC 24 |
Sep 18 02:29:47 PM UTC 24 |
7545858089 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_cfg_cmd.840276229 |
|
|
Sep 18 02:29:45 PM UTC 24 |
Sep 18 02:29:52 PM UTC 24 |
678658080 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_all.733577780 |
|
|
Sep 18 02:29:14 PM UTC 24 |
Sep 18 02:29:54 PM UTC 24 |
7733017292 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode.2622777245 |
|
|
Sep 18 02:29:47 PM UTC 24 |
Sep 18 02:29:56 PM UTC 24 |
1826224792 ps |
| T269 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_upload.190220718 |
|
|
Sep 18 02:29:32 PM UTC 24 |
Sep 18 02:29:58 PM UTC 24 |
26891647619 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.929324533 |
|
|
Sep 18 02:28:05 PM UTC 24 |
Sep 18 02:30:01 PM UTC 24 |
4538216959 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.2457450374 |
|
|
Sep 18 02:26:58 PM UTC 24 |
Sep 18 02:30:01 PM UTC 24 |
33000910999 ps |
| T36 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_stress_all.2350242834 |
|
|
Sep 18 02:29:06 PM UTC 24 |
Sep 18 02:30:07 PM UTC 24 |
124080388660 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.827384519 |
|
|
Sep 18 02:29:56 PM UTC 24 |
Sep 18 02:30:09 PM UTC 24 |
3281472603 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_alert_test.618664106 |
|
|
Sep 18 02:30:08 PM UTC 24 |
Sep 18 02:30:10 PM UTC 24 |
11538836 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_csb_read.1591353695 |
|
|
Sep 18 02:30:09 PM UTC 24 |
Sep 18 02:30:11 PM UTC 24 |
72664217 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.807650592 |
|
|
Sep 18 02:30:13 PM UTC 24 |
Sep 18 02:30:24 PM UTC 24 |
2123212149 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.437680667 |
|
|
Sep 18 02:30:25 PM UTC 24 |
Sep 18 02:30:27 PM UTC 24 |
131607459 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_rw.2064756384 |
|
|
Sep 18 02:30:28 PM UTC 24 |
Sep 18 02:30:31 PM UTC 24 |
71741720 ps |
| T145 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.640087448 |
|
|
Sep 18 02:29:54 PM UTC 24 |
Sep 18 02:30:36 PM UTC 24 |
12465184694 ps |
| T268 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.702121588 |
|
|
Sep 18 02:30:31 PM UTC 24 |
Sep 18 02:30:37 PM UTC 24 |
1225844913 ps |
| T187 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_all.3275899884 |
|
|
Sep 18 02:28:37 PM UTC 24 |
Sep 18 02:30:39 PM UTC 24 |
28804356323 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_all.1086466541 |
|
|
Sep 18 02:30:15 PM UTC 24 |
Sep 18 02:30:41 PM UTC 24 |
1524494178 ps |
| T146 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.2622232505 |
|
|
Sep 18 02:26:18 PM UTC 24 |
Sep 18 02:30:43 PM UTC 24 |
26215211400 ps |
| T212 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_intercept.4072231169 |
|
|
Sep 18 02:30:38 PM UTC 24 |
Sep 18 02:30:48 PM UTC 24 |
2455446817 ps |
| T280 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.1322075602 |
|
|
Sep 18 02:30:37 PM UTC 24 |
Sep 18 02:30:49 PM UTC 24 |
981139979 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.751287567 |
|
|
Sep 18 02:30:50 PM UTC 24 |
Sep 18 02:30:52 PM UTC 24 |
37360824 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.1639847713 |
|
|
Sep 18 02:30:53 PM UTC 24 |
Sep 18 02:30:59 PM UTC 24 |
604823099 ps |
| T48 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.3656352974 |
|
|
Sep 18 02:29:06 PM UTC 24 |
Sep 18 02:30:59 PM UTC 24 |
5525022869 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_cfg_cmd.1094950234 |
|
|
Sep 18 02:30:45 PM UTC 24 |
Sep 18 02:31:01 PM UTC 24 |
6532107525 ps |
| T299 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_mailbox.3258073884 |
|
|
Sep 18 02:30:40 PM UTC 24 |
Sep 18 02:31:03 PM UTC 24 |
4042928607 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_alert_test.1063782843 |
|
|
Sep 18 02:31:04 PM UTC 24 |
Sep 18 02:31:07 PM UTC 24 |
88538285 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_csb_read.821805866 |
|
|
Sep 18 02:31:07 PM UTC 24 |
Sep 18 02:31:09 PM UTC 24 |
26398864 ps |
| T209 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_intercept.529127684 |
|
|
Sep 18 02:32:29 PM UTC 24 |
Sep 18 02:32:41 PM UTC 24 |
401019257 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_all.711755482 |
|
|
Sep 18 02:27:58 PM UTC 24 |
Sep 18 02:31:10 PM UTC 24 |
16163128554 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.1344199796 |
|
|
Sep 18 02:28:38 PM UTC 24 |
Sep 18 02:31:12 PM UTC 24 |
36246393139 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.1157997390 |
|
|
Sep 18 02:31:11 PM UTC 24 |
Sep 18 02:31:14 PM UTC 24 |
1413213117 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode.1191407033 |
|
|
Sep 18 02:30:49 PM UTC 24 |
Sep 18 02:31:15 PM UTC 24 |
6389545012 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_upload.740432059 |
|
|
Sep 18 02:30:41 PM UTC 24 |
Sep 18 02:31:18 PM UTC 24 |
6019262881 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.2664536187 |
|
|
Sep 18 02:31:14 PM UTC 24 |
Sep 18 02:31:18 PM UTC 24 |
32698698 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.1073666957 |
|
|
Sep 18 02:31:10 PM UTC 24 |
Sep 18 02:31:20 PM UTC 24 |
2542942293 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_all.1258855952 |
|
|
Sep 18 02:31:11 PM UTC 24 |
Sep 18 02:31:20 PM UTC 24 |
2214301496 ps |
| T49 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.886597568 |
|
|
Sep 18 02:29:04 PM UTC 24 |
Sep 18 02:31:22 PM UTC 24 |
21630332643 ps |
| T67 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.1809813972 |
|
|
Sep 18 02:29:59 PM UTC 24 |
Sep 18 02:31:23 PM UTC 24 |
3410332616 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_mailbox.2983679166 |
|
|
Sep 18 02:31:19 PM UTC 24 |
Sep 18 02:31:23 PM UTC 24 |
297578236 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.2804502330 |
|
|
Sep 18 02:27:58 PM UTC 24 |
Sep 18 02:31:25 PM UTC 24 |
40896616887 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_rw.3880784014 |
|
|
Sep 18 02:31:13 PM UTC 24 |
Sep 18 02:31:26 PM UTC 24 |
961515693 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.2670564472 |
|
|
Sep 18 02:26:26 PM UTC 24 |
Sep 18 02:31:27 PM UTC 24 |
113812127943 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_cfg_cmd.660313678 |
|
|
Sep 18 02:31:21 PM UTC 24 |
Sep 18 02:31:32 PM UTC 24 |
2007194301 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.4205571259 |
|
|
Sep 18 02:31:15 PM UTC 24 |
Sep 18 02:31:38 PM UTC 24 |
2559865379 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.1758727697 |
|
|
Sep 18 02:31:24 PM UTC 24 |
Sep 18 02:31:40 PM UTC 24 |
3169315908 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_alert_test.3965629401 |
|
|
Sep 18 02:31:39 PM UTC 24 |
Sep 18 02:31:41 PM UTC 24 |
120257473 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_csb_read.3762403615 |
|
|
Sep 18 02:31:41 PM UTC 24 |
Sep 18 02:31:43 PM UTC 24 |
15187549 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.3018370477 |
|
|
Sep 18 02:31:45 PM UTC 24 |
Sep 18 02:31:47 PM UTC 24 |
299144639 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.1092237400 |
|
|
Sep 18 02:31:43 PM UTC 24 |
Sep 18 02:31:49 PM UTC 24 |
663230174 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_upload.1847296272 |
|
|
Sep 18 02:31:21 PM UTC 24 |
Sep 18 02:31:52 PM UTC 24 |
19226462806 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_rw.111491392 |
|
|
Sep 18 02:31:48 PM UTC 24 |
Sep 18 02:31:52 PM UTC 24 |
99229232 ps |
| T186 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.1946888232 |
|
|
Sep 18 02:30:01 PM UTC 24 |
Sep 18 02:31:54 PM UTC 24 |
30225645041 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.2711902525 |
|
|
Sep 18 02:29:03 PM UTC 24 |
Sep 18 02:32:02 PM UTC 24 |
38361784486 ps |
| T225 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_intercept.3292225924 |
|
|
Sep 18 02:31:18 PM UTC 24 |
Sep 18 02:32:06 PM UTC 24 |
4417389256 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_all.642711317 |
|
|
Sep 18 02:31:44 PM UTC 24 |
Sep 18 02:32:06 PM UTC 24 |
1226887049 ps |
| T278 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_intercept.2922981297 |
|
|
Sep 18 02:31:52 PM UTC 24 |
Sep 18 02:32:06 PM UTC 24 |
1040902226 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_cfg_cmd.91943731 |
|
|
Sep 18 02:32:03 PM UTC 24 |
Sep 18 02:32:09 PM UTC 24 |
265777923 ps |
| T283 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.3509359873 |
|
|
Sep 18 02:31:50 PM UTC 24 |
Sep 18 02:32:12 PM UTC 24 |
3486907975 ps |
| T300 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.1643003327 |
|
|
Sep 18 02:31:49 PM UTC 24 |
Sep 18 02:32:13 PM UTC 24 |
4416104126 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode.1283666468 |
|
|
Sep 18 02:32:07 PM UTC 24 |
Sep 18 02:32:17 PM UTC 24 |
529603845 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.77311115 |
|
|
Sep 18 02:32:14 PM UTC 24 |
Sep 18 02:32:20 PM UTC 24 |
445828962 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_stress_all.2390484720 |
|
|
Sep 18 02:32:18 PM UTC 24 |
Sep 18 02:32:21 PM UTC 24 |
339538098 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.735236079 |
|
|
Sep 18 02:32:07 PM UTC 24 |
Sep 18 02:32:22 PM UTC 24 |
707735714 ps |
| T270 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_upload.110758895 |
|
|
Sep 18 02:31:55 PM UTC 24 |
Sep 18 02:32:23 PM UTC 24 |
14017702360 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_alert_test.374179371 |
|
|
Sep 18 02:32:21 PM UTC 24 |
Sep 18 02:32:24 PM UTC 24 |
13974998 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_csb_read.1172360220 |
|
|
Sep 18 02:32:22 PM UTC 24 |
Sep 18 02:32:24 PM UTC 24 |
27904165 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.2625436209 |
|
|
Sep 18 02:32:25 PM UTC 24 |
Sep 18 02:32:28 PM UTC 24 |
149567274 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_rw.4062229528 |
|
|
Sep 18 02:32:26 PM UTC 24 |
Sep 18 02:32:29 PM UTC 24 |
18727234 ps |
| T294 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_mailbox.4029690548 |
|
|
Sep 18 02:31:53 PM UTC 24 |
Sep 18 02:32:34 PM UTC 24 |
2935226679 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.759295700 |
|
|
Sep 18 02:32:24 PM UTC 24 |
Sep 18 02:32:34 PM UTC 24 |
4215306256 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_upload.1005112174 |
|
|
Sep 18 02:32:35 PM UTC 24 |
Sep 18 02:32:39 PM UTC 24 |
42512849 ps |
| T243 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_all.1093314419 |
|
|
Sep 18 02:29:03 PM UTC 24 |
Sep 18 02:32:42 PM UTC 24 |
45558287079 ps |
| T287 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode_ignore_cmds.1251783148 |
|
|
Sep 18 02:32:07 PM UTC 24 |
Sep 18 02:32:44 PM UTC 24 |
4105923796 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_cfg_cmd.1108826312 |
|
|
Sep 18 02:32:35 PM UTC 24 |
Sep 18 02:32:44 PM UTC 24 |
344339892 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_all.2460298354 |
|
|
Sep 18 02:32:25 PM UTC 24 |
Sep 18 02:32:46 PM UTC 24 |
1394161832 ps |
| T295 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_cmd_filtering.2283464656 |
|
|
Sep 18 02:32:28 PM UTC 24 |
Sep 18 02:32:47 PM UTC 24 |
1202329689 ps |
| T99 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.438747885 |
|
|
Sep 18 02:24:52 PM UTC 24 |
Sep 18 02:32:48 PM UTC 24 |
94578432847 ps |
| T220 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.3131122467 |
|
|
Sep 18 02:32:28 PM UTC 24 |
Sep 18 02:32:49 PM UTC 24 |
11600801415 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_alert_test.3436671637 |
|
|
Sep 18 02:32:47 PM UTC 24 |
Sep 18 02:32:50 PM UTC 24 |
93806738 ps |
| T164 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_stress_all.1963068376 |
|
|
Sep 18 02:34:20 PM UTC 24 |
Sep 18 02:34:23 PM UTC 24 |
658585473 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_read_buffer_direct.1366620763 |
|
|
Sep 18 02:32:43 PM UTC 24 |
Sep 18 02:32:52 PM UTC 24 |
1249028956 ps |
| T175 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_csb_read.2723947845 |
|
|
Sep 18 02:32:50 PM UTC 24 |
Sep 18 02:32:52 PM UTC 24 |
13120964 ps |
| T176 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.1765369974 |
|
|
Sep 18 02:30:59 PM UTC 24 |
Sep 18 02:32:54 PM UTC 24 |
7839410988 ps |
| T177 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.4111642403 |
|
|
Sep 18 02:25:02 PM UTC 24 |
Sep 18 02:32:54 PM UTC 24 |
166153537411 ps |
| T178 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_sts_read.370879102 |
|
|
Sep 18 02:32:53 PM UTC 24 |
Sep 18 02:32:55 PM UTC 24 |
204433902 ps |
| T179 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_rw.2257741653 |
|
|
Sep 18 02:32:53 PM UTC 24 |
Sep 18 02:32:56 PM UTC 24 |
72647168 ps |
| T180 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_read_hw_reg.2280948324 |
|
|
Sep 18 02:32:51 PM UTC 24 |
Sep 18 02:33:00 PM UTC 24 |
6404797340 ps |
| T181 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.1843532158 |
|
|
Sep 18 02:30:59 PM UTC 24 |
Sep 18 02:33:01 PM UTC 24 |
13401175947 ps |
| T182 |
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_pass_addr_payload_swap.443606333 |
|
|
Sep 18 02:32:55 PM UTC 24 |
Sep 18 02:33:04 PM UTC 24 |
802206777 ps |