Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	35317	1			T6	4		T10	72		T12	4
auto[SpiFlashAddrCfg]	8215	1			T12	16		T13	4		T16	7
auto[SpiFlashAddr3b]	10060	1			T6	4		T9	6		T10	6
auto[SpiFlashAddr4b]	8241	1			T10	2		T16	7		T41	4

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34576

1

T6

8

T9

6

T10

80

auto[1]

27257

1

T12

22

T16

18

T18

6

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33231

1

T6

6

T12

16

T13

3

auto[1]

28602

1

T6

2

T9

6

T10

80

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	40339	1			T6	6		T10	74		T12	4
values[1]	1141	1			T16	2		T17	4		T29	1
values[2]	1608	1			T13	3		T41	2		T29	4
values[3]	1623	1			T16	3		T29	2		T55	2
values[4]	1555	1			T6	2		T45	5		T183	2
values[5]	1629	1			T12	2		T16	1		T29	1
values[6]	1575	1			T12	6		T16	5		T55	2
values[7]	1517	1			T16	1		T41	2		T29	3
values[8]	10846	1			T9	6		T10	6		T12	10

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32278

1

T6

8

T9

6

T10

80

auto[1]

29555

1

T13

4

T38

8

T29

41

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

58346

1

T6

6

T9

6

T10

78

write

3487

1

T6

2

T10

2

T16

3

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

21064

1

T6

4

T9

4

T10

4

valids[0x1]

40769

1

T6

4

T9

2

T10

76

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1783	1			T29	2		T45	7		T57	2
internal_process_ops[0x5a]	1743	1			T9	2		T10	2		T16	1
internal_process_ops[0x05]	20022	1			T6	2		T10	72		T16	2
internal_process_ops[0x35]	1680	1			T12	4		T16	1		T18	2
internal_process_ops[0x15]	1718	1			T16	2		T41	2		T45	6
internal_process_ops[0x03]	1190	1			T12	6		T16	1		T17	4
internal_process_ops[0x0b]	1153	1			T13	1		T16	3		T38	2
internal_process_ops[0x3b]	1215	1			T9	4		T12	2		T16	1
internal_process_ops[0x6b]	1168	1			T16	1		T29	1		T45	6
internal_process_ops[0xbb]	1149	1			T13	3		T16	2		T41	2
internal_process_ops[0xeb]	1125	1			T16	1		T38	3		T45	4

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

60173

1

T6

8

T9

6

T10

80

auto[1]

1660

1

T16

1

T18

2

T45

5

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59269

1

T6

8

T9

6

T10

78

auto[1]

2564

1

T10

2

T41

6

T29

1

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10073

1

T6

4

T10

72

T16

10

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6754

1

T12

4

T16

5

T18

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2209

1

T41

2

T55

4

T45

7

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

2041

1

T12

16

T16

4

T18

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2764

1

T6

2

T9

6

T10

6

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2485

1

T12

2

T16

3

T45

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2289

1

T16

1

T41

4

T55

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2017

1

T16

6

T45

14

T183

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

128

1

T55

2

T60

1

T47

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

81

1

T58

1

T60

2

T47

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

97

1

T45

3

T64

1

T138

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

119

1

T45

2

T63

2

T60

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

110

1

T16

2

T41

6

T184

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

97

1

T16

1

T60

2

T185

6

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

102

1

T62

1

T60

7

T47

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

129

1

T45

1

T61

2

T60

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

133

1

T6

2

T60

2

T64

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

78

1

T62

2

T64

2

T47

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

109

1

T62

2

T47

1

T185

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

109

1

T18

2

T64

1

T47

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

98

1

T10

2

T45

1

T60

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

69

1

T62

1

T60

3

T64

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

86

1

T45

1

T64

1

T47

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

101

1

T45

2

T60

1

T47

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10542

1

T29

9

T50

63

T51

31

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7017

1

T29

4

T50

39

T51

15

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1488

1

T13

4

T38

2

T29

5

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1584

1

T29

11

T50

25

T51

9

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2004

1

T38

2

T29

4

T110

4

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1938

1

T29

5

T50

21

T51

8

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1531

1

T38

4

T29

1

T50

6

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1610

1

T50

14

T51

6

T79

10

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

123

1

T79

3

T101

5

T137

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

111

1

T51

1

T79

3

T102

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

146

1

T29

1

T50

3

T34

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

126

1

T50

1

T51

2

T34

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

99

1

T50

2

T34

1

T146

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

129

1

T51

2

T34

1

T101

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

120

1

T50

1

T51

2

T79

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

107

1

T34

3

T137

2

T186

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

119

1

T79

1

T34

1

T101

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

108

1

T51

1

T79

1

T34

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

119

1

T50

1

T51

2

T34

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

94

1

T50

1

T34

1

T101

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

104

1

T29

1

T51

1

T187

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

89

1

T50

1

T79

2

T34

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

134

1

T50

2

T51

1

T79

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

113

1

T79

2

T34

2

T102

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4254	1			T6	2		T16	9		T55	2
auto[0]	values[0]	valids[0x1]	15561	1			T6	4		T10	74		T12	4
auto[0]	values[1]	valids[0x1]	621	1			T16	2		T17	4		T45	3
auto[0]	values[2]	valids[0x0]	586	1			T56	2		T45	6		T109	2
auto[0]	values[2]	valids[0x1]	329	1			T41	2		T45	2		T58	3
auto[0]	values[3]	valids[0x0]	622	1			T16	3		T55	2		T45	3
auto[0]	values[3]	valids[0x1]	311	1			T188	2		T62	2		T189	2
auto[0]	values[4]	valids[0x0]	607	1			T6	2		T45	3		T183	2
auto[0]	values[4]	valids[0x1]	300	1			T45	2		T60	6		T64	1
auto[0]	values[5]	valids[0x0]	572	1			T12	2		T16	1		T45	2
auto[0]	values[5]	valids[0x1]	362	1			T45	4		T111	4		T58	4
auto[0]	values[6]	valids[0x0]	564	1			T16	4		T55	2		T109	2
auto[0]	values[6]	valids[0x1]	376	1			T12	6		T16	1		T45	3
auto[0]	values[7]	valids[0x0]	599	1			T16	1		T41	2		T45	1
auto[0]	values[7]	valids[0x1]	294	1			T45	2		T58	3		T62	2
auto[0]	values[8]	valids[0x0]	3949	1			T9	4		T10	4		T12	6
auto[0]	values[8]	valids[0x1]	2371	1			T9	2		T10	2		T12	4
auto[1]	values[0]	valids[0x0]	4201	1			T29	6		T50	40		T51	18
auto[1]	values[0]	valids[0x1]	16323	1			T13	1		T38	2		T29	12
auto[1]	values[1]	valids[0x1]	520	1			T29	1		T50	1		T51	3
auto[1]	values[2]	valids[0x0]	422	1			T13	3		T29	4		T50	1
auto[1]	values[2]	valids[0x1]	271	1			T50	5		T51	2		T79	1
auto[1]	values[3]	valids[0x0]	420	1			T29	2		T50	3		T51	3
auto[1]	values[3]	valids[0x1]	270	1			T50	5		T51	2		T34	6
auto[1]	values[4]	valids[0x0]	417	1			T52	2		T50	4		T79	3
auto[1]	values[4]	valids[0x1]	231	1			T50	1		T51	2		T34	2
auto[1]	values[5]	valids[0x0]	425	1			T29	1		T110	4		T50	6
auto[1]	values[5]	valids[0x1]	270	1			T50	5		T79	2		T34	1
auto[1]	values[6]	valids[0x0]	382	1			T50	4		T51	6		T190	2
auto[1]	values[6]	valids[0x1]	253	1			T79	3		T34	1		T102	2
auto[1]	values[7]	valids[0x0]	348	1			T29	3		T52	1		T50	5
auto[1]	values[7]	valids[0x1]	276	1			T50	7		T79	8		T34	5
auto[1]	values[8]	valids[0x0]	2696	1			T38	4		T29	6		T52	1
auto[1]	values[8]	valids[0x1]	1830	1			T38	2		T29	6		T110	1