Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3536612

1

T6

1

T8

1530

T9

6945

auto[1]

30767

1

T10

72

T41

170

T29

1

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

897994

1

T6

1

T8

1530

T9

6945

auto[1]

2669385

1

T10

72

T16

2637

T41

682

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	657581	1			T6	1		T8	274		T9	1237
auto[524288:1048575]	389122	1			T9	277		T13	2		T16	9
auto[1048576:1572863]	444203	1			T9	1158		T16	518		T17	63
auto[1572864:2097151]	416626	1			T8	216		T9	1347		T16	2
auto[2097152:2621439]	421327	1			T9	1746		T13	5		T37	38
auto[2621440:3145727]	436308	1			T8	335		T13	1289		T17	49
auto[3145728:3670015]	362746	1			T9	1180		T13	981		T17	21
auto[3670016:4194303]	439466	1			T8	705		T16	515		T17	42

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2707209

1

T6

1

T8

69

T9

17

auto[1]

860170

1

T8

1461

T9

6928

T10

1

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3073367

1

T6

1

T8

1530

T9

6945

auto[1]

494012

1

T16

517

T29

261

T45

1078

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	218476	1			T6	1		T8	274		T9	1237
auto[0]	auto[0]	auto[0:524287]	auto[1]	354837	1			T10	2		T16	1603		T41	518
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	82813	1			T9	277		T13	2		T16	4
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	259532	1			T16	5		T45	128		T96	19
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	112470	1			T9	1158		T16	1		T17	63
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	261681	1			T96	532		T58	6		T62	256
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	81290	1			T8	216		T9	1347		T16	2
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	268634	1			T45	2996		T96	3005		T62	623
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	82915	1			T9	1746		T13	5		T37	38
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	267244	1			T45	2624		T96	3249		T58	5251
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	106262	1			T8	335		T13	1289		T17	49
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	279701	1			T45	2942		T50	387		T62	901
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	76590	1			T9	1180		T13	981		T17	21
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	225212	1			T29	1		T45	107		T96	2509
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	121393	1			T8	705		T16	3		T17	42
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	248053	1			T16	512		T29	128		T45	3422
auto[0]	auto[1]	auto[0:524287]	auto[0]	1705	1			T45	30		T95	8		T203	4
auto[0]	auto[1]	auto[0:524287]	auto[1]	78588	1			T45	1029		T60	3159		T64	570
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	2654	1			T50	2		T51	1		T79	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	39826	1			T50	1		T51	128		T79	4
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	2961	1			T29	3		T50	3		T51	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	62874	1			T16	517		T29	256		T51	41
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	747	1			T203	10		T60	9		T34	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	62875	1			T51	219		T137	343		T138	1029
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	1032	1			T45	2		T95	1		T58	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	66495	1			T58	2186		T50	2		T51	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	894	1			T95	22		T50	2		T62	12
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	45893	1			T50	1		T64	770		T48	2999
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	766	1			T29	2		T45	3		T79	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	55920	1			T79	214		T60	134		T47	128
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	723	1			T45	14		T95	4		T58	3
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	65556	1			T58	1		T34	513		T137	256
auto[1]	auto[0]	auto[0:524287]	auto[0]	508	1			T10	2		T41	6		T45	4
auto[1]	auto[0]	auto[0:524287]	auto[1]	2826	1			T10	70		T41	164		T64	3
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	424	1			T50	2		T60	4		T64	2
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	3559	1			T50	7		T60	2		T64	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	477	1			T45	6		T58	1		T51	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	3139	1			T58	15		T185	11		T102	640
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	331	1			T51	2		T79	1		T60	14
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2210	1			T79	5		T60	923		T64	8
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	416	1			T45	20		T50	2		T79	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2674	1			T45	131		T50	2		T79	73
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	447	1			T45	3		T50	1		T62	5
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2554	1			T45	24		T50	4		T79	82
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	422	1			T29	1		T45	3		T50	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	3164	1			T45	21		T60	512		T34	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	521	1			T45	2		T50	2		T51	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2592	1			T51	1		T79	167		T64	1
auto[1]	auto[1]	auto[0:524287]	auto[0]	135	1			T60	11		T64	1		T34	4
auto[1]	auto[1]	auto[0:524287]	auto[1]	506	1			T64	8		T34	8		T213	45
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	92	1			T50	1		T34	3		T101	18
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	222	1			T50	2		T34	4		T101	18
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	100	1			T60	5		T101	9		T251	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	501	1			T251	4		T67	61		T243	18
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	71	1			T138	1		T146	1		T49	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	468	1			T138	5		T146	8		T49	49
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	104	1			T58	1		T51	2		T47	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	447	1			T58	11		T47	3		T250	24
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	84	1			T50	1		T64	1		T213	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	473	1			T213	5		T49	1		T86	58
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	87	1			T60	17		T67	5		T85	10
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	585	1			T60	253		T67	20		T85	10
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	84	1			T58	1		T34	1		T85	6
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	544	1			T58	9		T243	15		T39	1

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2193528	1			T6	1		T8	69		T9	17
auto[0]	auto[0]	auto[1]	853575	1			T8	1461		T9	6928		T10	1
auto[0]	auto[1]	auto[0]	483604	1			T16	517		T29	261		T45	1078
auto[0]	auto[1]	auto[1]	5905	1			T95	23		T58	1		T203	9
auto[1]	auto[0]	auto[0]	25689	1			T10	72		T41	170		T29	1
auto[1]	auto[0]	auto[1]	575	1			T45	8		T50	2		T62	1
auto[1]	auto[1]	auto[0]	4388	1			T58	22		T50	4		T51	2
auto[1]	auto[1]	auto[1]	115	1			T60	4		T34	1		T101	5