Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3537414	1			T1	1		T2	1		T3	2
all_pins[1]	3537414	1			T1	1		T2	1		T3	2
all_pins[2]	3537414	1			T1	1		T2	1		T3	2
all_pins[3]	3537414	1			T1	1		T2	1		T3	2
all_pins[4]	3537414	1			T1	1		T2	1		T3	2
all_pins[5]	3537414	1			T1	1		T2	1		T3	2
all_pins[6]	3537414	1			T1	1		T2	1		T3	2
all_pins[7]	3537414	1			T1	1		T2	1		T3	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	28270406	1			T1	8		T2	8		T3	16
values[0x1]	28906	1			T20	17		T23	18		T34	388
transitions[0x0=>0x1]	27230	1			T20	15		T23	15		T34	385
transitions[0x1=>0x0]	27238	1			T20	15		T23	15		T34	385

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	3536712	1			T1	1		T2	1		T3	2
all_pins[0]	values[0x1]	702	1			T23	3		T34	4		T35	8
all_pins[0]	transitions[0x0=>0x1]	431	1			T23	3		T34	4		T35	7
all_pins[0]	transitions[0x1=>0x0]	210	1			T20	1		T23	1		T34	2
all_pins[1]	values[0x0]	3536933	1			T1	1		T2	1		T3	2
all_pins[1]	values[0x1]	481	1			T20	1		T23	1		T34	2
all_pins[1]	transitions[0x0=>0x1]	350	1			T20	1		T23	1		T34	2
all_pins[1]	transitions[0x1=>0x0]	222	1			T20	2		T23	3		T34	2
all_pins[2]	values[0x0]	3537061	1			T1	1		T2	1		T3	2
all_pins[2]	values[0x1]	353	1			T20	2		T23	3		T34	2
all_pins[2]	transitions[0x0=>0x1]	315	1			T20	2		T23	2		T34	2
all_pins[2]	transitions[0x1=>0x0]	144	1			T20	3		T23	4		T34	2
all_pins[3]	values[0x0]	3537232	1			T1	1		T2	1		T3	2
all_pins[3]	values[0x1]	182	1			T20	3		T23	5		T34	2
all_pins[3]	transitions[0x0=>0x1]	130	1			T20	3		T23	4		T34	2
all_pins[3]	transitions[0x1=>0x0]	147	1			T20	2		T23	2		T34	3
all_pins[4]	values[0x0]	3537215	1			T1	1		T2	1		T3	2
all_pins[4]	values[0x1]	199	1			T20	2		T23	3		T34	3
all_pins[4]	transitions[0x0=>0x1]	159	1			T20	1		T23	3		T34	3
all_pins[4]	transitions[0x1=>0x0]	2909	1			T20	2		T34	367		T35	3
all_pins[5]	values[0x0]	3534465	1			T1	1		T2	1		T3	2
all_pins[5]	values[0x1]	2949	1			T20	3		T34	367		T35	3
all_pins[5]	transitions[0x0=>0x1]	1902	1			T20	2		T34	367		T35	2
all_pins[5]	transitions[0x1=>0x0]	22812	1			T20	1		T23	1		T34	2
all_pins[6]	values[0x0]	3513555	1			T1	1		T2	1		T3	2
all_pins[6]	values[0x1]	23859	1			T20	2		T23	1		T34	2
all_pins[6]	transitions[0x0=>0x1]	23817	1			T20	2		T34	1		T164	3
all_pins[6]	transitions[0x1=>0x0]	139	1			T20	4		T23	1		T34	5
all_pins[7]	values[0x0]	3537233	1			T1	1		T2	1		T3	2
all_pins[7]	values[0x1]	181	1			T20	4		T23	2		T34	6
all_pins[7]	transitions[0x0=>0x1]	126	1			T20	4		T23	2		T34	4
all_pins[7]	transitions[0x1=>0x0]	655	1			T23	3		T34	2		T35	4