Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18129

1

T6

8

T9

6

T10

80

auto[1]

14149

1

T12

22

T16

18

T18

6

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4421	1			T109	20		T123	2		T188	14
values[1]	3865	1			T62	20		T184	16		T60	40
values[2]	3915	1			T6	8		T16	40		T45	20
values[3]	3878	1			T10	80		T17	4		T95	24
values[4]	3990	1			T18	6		T45	40		T223	10
values[5]	3651	1			T12	22		T55	12		T56	8
values[6]	4591	1			T41	188		T45	20		T111	18
values[7]	3967	1			T9	6		T45	20		T100	22

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3869	1			T45	20		T96	12		T111	18
values[1]	4414	1			T45	20		T58	32		T189	12
values[2]	4245	1			T55	12		T56	8		T123	2
values[3]	2907	1			T16	20		T109	20		T223	10
values[4]	4651	1			T6	8		T45	20		T54	8
values[5]	3941	1			T9	6		T10	80		T17	4
values[6]	3784	1			T45	20		T58	30		T64	46
values[7]	4467	1			T12	22		T16	20		T18	6

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	228	1			T252	2		T87	45		T218	13
auto[0]	values[0]	values[1]	314	1			T185	13		T99	13		T253	48
auto[0]	values[0]	values[2]	231	1			T123	2		T47	26		T185	6
auto[0]	values[0]	values[3]	287	1			T109	20		T138	10		T176	16
auto[0]	values[0]	values[4]	266	1			T49	8		T71	14		T254	2
auto[0]	values[0]	values[5]	326	1			T188	14		T47	11		T228	14
auto[0]	values[0]	values[6]	323	1			T64	8		T49	15		T99	12
auto[0]	values[0]	values[7]	366	1			T60	12		T255	18		T228	9
auto[0]	values[1]	values[0]	288	1			T62	10		T184	16		T185	2
auto[0]	values[1]	values[1]	261	1			T60	13		T209	12		T176	53
auto[0]	values[1]	values[2]	173	1			T185	10		T49	7		T217	12
auto[0]	values[1]	values[3]	123	1			T145	12		T256	11		T238	13
auto[0]	values[1]	values[4]	367	1			T257	4		T39	12		T258	12
auto[0]	values[1]	values[5]	303	1			T47	10		T138	43		T87	10
auto[0]	values[1]	values[6]	283	1			T213	34		T49	14		T68	11
auto[0]	values[1]	values[7]	230	1			T60	11		T185	15		T248	12
auto[0]	values[2]	values[0]	323	1			T45	14		T96	12		T60	9
auto[0]	values[2]	values[1]	215	1			T259	4		T165	14		T260	20
auto[0]	values[2]	values[2]	226	1			T60	9		T145	6		T177	8
auto[0]	values[2]	values[3]	328	1			T16	9		T62	10		T222	24
auto[0]	values[2]	values[4]	400	1			T6	8		T54	8		T58	8
auto[0]	values[2]	values[5]	184	1			T48	10		T261	16		T230	37
auto[0]	values[2]	values[6]	296	1			T177	9		T68	18		T39	6
auto[0]	values[2]	values[7]	251	1			T16	13		T262	2		T39	14
auto[0]	values[3]	values[0]	165	1			T263	6		T64	10		T49	12
auto[0]	values[3]	values[1]	292	1			T176	6		T68	11		T256	12
auto[0]	values[3]	values[2]	351	1			T264	4		T138	10		T49	37
auto[0]	values[3]	values[3]	330	1			T60	9		T73	12		T176	11
auto[0]	values[3]	values[4]	318	1			T57	14		T58	9		T60	11
auto[0]	values[3]	values[5]	351	1			T10	80		T17	4		T95	24
auto[0]	values[3]	values[6]	204	1			T58	10		T64	15		T185	18
auto[0]	values[3]	values[7]	211	1			T47	10		T185	43		T74	6
auto[0]	values[4]	values[0]	233	1			T265	4		T227	22		T177	19
auto[0]	values[4]	values[1]	428	1			T138	10		T49	14		T228	8
auto[0]	values[4]	values[2]	423	1			T203	8		T210	9		T266	10
auto[0]	values[4]	values[3]	151	1			T223	10		T256	16		T267	2
auto[0]	values[4]	values[4]	335	1			T45	13		T60	13		T185	14
auto[0]	values[4]	values[5]	230	1			T45	8		T47	13		T176	24
auto[0]	values[4]	values[6]	260	1			T47	14		T268	4		T48	15
auto[0]	values[4]	values[7]	294	1			T97	10		T60	9		T73	28
auto[0]	values[5]	values[0]	193	1			T269	10		T73	30		T99	12
auto[0]	values[5]	values[1]	298	1			T45	14		T58	26		T270	10
auto[0]	values[5]	values[2]	274	1			T55	12		T56	8		T271	4
auto[0]	values[5]	values[3]	180	1			T73	10		T272	2		T39	12
auto[0]	values[5]	values[4]	358	1			T228	25		T208	16		T39	13
auto[0]	values[5]	values[5]	265	1			T60	15		T64	11		T177	16
auto[0]	values[5]	values[6]	214	1			T273	2		T208	11		T232	12
auto[0]	values[5]	values[7]	331	1			T47	20		T185	6		T99	14
auto[0]	values[6]	values[0]	317	1			T111	18		T213	12		T165	10
auto[0]	values[6]	values[1]	353	1			T185	8		T221	8		T225	14
auto[0]	values[6]	values[2]	362	1			T62	8		T185	42		T138	3
auto[0]	values[6]	values[3]	314	1			T274	34		T275	18		T276	18
auto[0]	values[6]	values[4]	337	1			T62	9		T60	11		T185	17
auto[0]	values[6]	values[5]	377	1			T41	188		T176	11		T39	21
auto[0]	values[6]	values[6]	252	1			T206	10		T212	12		T48	14
auto[0]	values[6]	values[7]	315	1			T45	15		T58	12		T49	10
auto[0]	values[7]	values[0]	271	1			T211	16		T245	8		T71	9
auto[0]	values[7]	values[1]	314	1			T189	12		T98	24		T253	12
auto[0]	values[7]	values[2]	281	1			T217	24		T277	10		T230	20
auto[0]	values[7]	values[3]	110	1			T278	8		T217	10		T215	11
auto[0]	values[7]	values[4]	225	1			T100	22		T244	8		T62	10
auto[0]	values[7]	values[5]	443	1			T9	6		T59	16		T279	16
auto[0]	values[7]	values[6]	316	1			T45	9		T224	7		T230	15
auto[0]	values[7]	values[7]	261	1			T64	23		T48	7		T49	8
auto[1]	values[0]	values[0]	360	1			T280	8		T87	5		T218	41
auto[1]	values[0]	values[1]	296	1			T185	23		T99	7		T253	10
auto[1]	values[0]	values[2]	201	1			T47	14		T185	35		T49	47
auto[1]	values[0]	values[3]	178	1			T138	15		T176	4		T177	11
auto[1]	values[0]	values[4]	300	1			T49	12		T71	6		T39	23
auto[1]	values[0]	values[5]	249	1			T47	9		T228	59		T39	12
auto[1]	values[0]	values[6]	234	1			T64	12		T49	41		T99	8
auto[1]	values[0]	values[7]	262	1			T63	2		T60	8		T228	21
auto[1]	values[1]	values[0]	165	1			T62	10		T185	18		T71	13
auto[1]	values[1]	values[1]	210	1			T60	7		T176	6		T208	42
auto[1]	values[1]	values[2]	421	1			T185	52		T49	51		T217	8
auto[1]	values[1]	values[3]	122	1			T145	8		T256	9		T238	7
auto[1]	values[1]	values[4]	194	1			T39	13		T258	8		T246	50
auto[1]	values[1]	values[5]	169	1			T47	14		T138	10		T87	15
auto[1]	values[1]	values[6]	182	1			T213	29		T49	6		T68	11
auto[1]	values[1]	values[7]	374	1			T60	9		T185	52		T99	10
auto[1]	values[2]	values[0]	205	1			T45	6		T60	11		T165	10
auto[1]	values[2]	values[1]	270	1			T165	8		T260	20		T281	9
auto[1]	values[2]	values[2]	276	1			T60	11		T145	14		T177	13
auto[1]	values[2]	values[3]	193	1			T16	11		T62	10		T71	6
auto[1]	values[2]	values[4]	264	1			T58	28		T64	19		T185	8
auto[1]	values[2]	values[5]	122	1			T48	20		T282	8		T230	7
auto[1]	values[2]	values[6]	201	1			T177	19		T68	3		T39	15
auto[1]	values[2]	values[7]	161	1			T16	7		T39	14		T256	12
auto[1]	values[3]	values[0]	301	1			T61	16		T64	12		T49	22
auto[1]	values[3]	values[1]	123	1			T176	14		T68	9		T256	8
auto[1]	values[3]	values[2]	298	1			T138	22		T49	13		T283	22
auto[1]	values[3]	values[3]	212	1			T60	11		T73	8		T176	9
auto[1]	values[3]	values[4]	229	1			T183	8		T58	11		T207	24
auto[1]	values[3]	values[5]	162	1			T48	12		T220	16		T210	5
auto[1]	values[3]	values[6]	194	1			T58	20		T64	11		T185	7
auto[1]	values[3]	values[7]	137	1			T47	10		T185	11		T281	12
auto[1]	values[4]	values[0]	161	1			T177	9		T228	17		T165	22
auto[1]	values[4]	values[1]	219	1			T138	10		T49	48		T228	12
auto[1]	values[4]	values[2]	145	1			T210	11		T233	9		T281	13
auto[1]	values[4]	values[3]	38	1			T256	4		T284	6		T285	5
auto[1]	values[4]	values[4]	219	1			T45	7		T60	7		T185	6
auto[1]	values[4]	values[5]	134	1			T45	12		T47	9		T176	14
auto[1]	values[4]	values[6]	190	1			T47	6		T48	5		T213	17
auto[1]	values[4]	values[7]	530	1			T18	6		T60	11		T73	18
auto[1]	values[5]	values[0]	163	1			T73	6		T99	8		T224	12
auto[1]	values[5]	values[1]	356	1			T45	6		T58	6		T286	6
auto[1]	values[5]	values[2]	119	1			T47	9		T287	7		T208	5
auto[1]	values[5]	values[3]	109	1			T73	17		T39	8		T238	10
auto[1]	values[5]	values[4]	174	1			T75	24		T228	9		T208	8
auto[1]	values[5]	values[5]	194	1			T60	5		T64	13		T177	4
auto[1]	values[5]	values[6]	210	1			T208	9		T232	30		T165	10
auto[1]	values[5]	values[7]	213	1			T12	22		T47	5		T185	14
auto[1]	values[6]	values[0]	219	1			T213	8		T165	14		T288	7
auto[1]	values[6]	values[1]	290	1			T185	12		T99	5		T208	5
auto[1]	values[6]	values[2]	226	1			T62	12		T185	2		T138	19
auto[1]	values[6]	values[3]	138	1			T289	4		T234	10		T290	18
auto[1]	values[6]	values[4]	400	1			T62	11		T60	9		T185	3
auto[1]	values[6]	values[5]	227	1			T176	9		T39	12		T230	37
auto[1]	values[6]	values[6]	219	1			T48	8		T49	64		T176	7
auto[1]	values[6]	values[7]	245	1			T45	5		T58	8		T49	10
auto[1]	values[7]	values[0]	277	1			T71	11		T208	10		T39	10
auto[1]	values[7]	values[1]	175	1			T253	8		T224	30		T230	10
auto[1]	values[7]	values[2]	238	1			T217	16		T230	11		T214	75
auto[1]	values[7]	values[3]	94	1			T217	10		T215	9		T40	16
auto[1]	values[7]	values[4]	265	1			T62	10		T213	95		T176	10
auto[1]	values[7]	values[5]	205	1			T217	7		T39	7		T238	13
auto[1]	values[7]	values[6]	206	1			T45	11		T224	13		T230	22
auto[1]	values[7]	values[7]	286	1			T64	8		T48	13		T49	29