Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

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Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	446	1			T16	1		T45	1		T109	14
auto[ReadAddrCrossIntoMailbox]	336	1			T16	1		T45	1		T111	2
auto[ReadAddrCrossOutOfMailbox]	331	1			T45	2		T111	4		T62	3
auto[ReadAddrCrossAllMailbox]	251	1			T45	1		T111	2		T62	1
auto[ReadAddrOutsideMailbox]	3940	1			T9	4		T12	8		T16	7

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2617

1

T9

2

T12

4

T16

8

auto[1]

2687

1

T9

2

T12

4

T16

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	904	1			T12	6		T16	1		T17	4
read_ops[0x0b]	881	1			T16	3		T45	5		T111	4
read_ops[0x3b]	907	1			T9	4		T12	2		T16	1
read_ops[0x6b]	906	1			T16	1		T45	6		T109	4
read_ops[0xbb]	859	1			T16	2		T41	2		T45	2
read_ops[0xeb]	847	1			T16	1		T45	4		T109	10

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	41	1			T64	1		T47	1		T48	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T185	2		T145	1		T73	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	31	1			T64	1		T185	1		T176	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T138	2		T49	1		T238	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	32	1			T111	1		T47	1		T208	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T111	1		T60	1		T48	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T47	1		T49	1		T229	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T138	1		T229	2		T217	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	311	1			T12	3		T16	1		T17	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	365	1			T12	3		T17	2		T41	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	39	1			T185	1		T248	1		T138	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T45	1		T64	1		T185	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T48	1		T49	1		T177	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	34	1			T217	1		T256	1		T230	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T45	1		T111	1		T262	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T111	1		T262	1		T49	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	25	1			T47	1		T177	1		T39	3
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T99	1		T292	2		T293	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	330	1			T16	2		T45	1		T111	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	328	1			T16	1		T45	2		T111	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T109	1		T245	1		T248	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	46	1			T109	1		T62	1		T245	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T185	1		T87	1		T214	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T47	1		T185	1		T208	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	33	1			T64	1		T145	1		T49	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	47	1			T62	2		T64	1		T185	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T49	1		T231	1		T256	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T45	1		T62	1		T213	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	347	1			T9	2		T12	1		T16	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	314	1			T9	2		T12	1		T57	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T16	1		T109	2		T245	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	46	1			T109	2		T60	1		T245	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T60	1		T48	1		T49	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T64	2		T49	1		T294	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T64	1		T48	1		T177	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T45	1		T47	2		T217	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	27	1			T47	1		T48	1		T99	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T185	1		T231	1		T229	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	332	1			T111	3		T57	1		T58	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	344	1			T45	5		T111	3		T57	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T209	1		T49	1		T225	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	42	1			T60	1		T64	1		T209	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T16	1		T111	1		T49	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T111	1		T62	1		T39	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	14	1			T87	1		T218	1		T168	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T64	1		T145	1		T48	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T111	1		T49	1		T87	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T111	1		T64	2		T217	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	342	1			T16	1		T41	1		T45	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	306	1			T41	1		T45	1		T109	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T109	4		T64	1		T47	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T109	4		T185	1		T73	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T185	1		T138	1		T48	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	38	1			T45	1		T60	1		T185	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T62	1		T64	1		T47	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	33	1			T48	1		T213	1		T49	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T294	1		T256	2		T246	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T185	1		T294	1		T39	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	312	1			T16	1		T109	1		T183	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	309	1			T45	3		T109	1		T183	1