Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4709	1			T16	20		T41	188		T45	20
values[1]	3724	1			T97	10		T60	20		T64	26
values[2]	3721	1			T6	8		T10	80		T95	24
values[3]	3419	1			T56	8		T45	20		T57	14
values[4]	4453	1			T109	20		T96	12		T62	20
values[5]	4180	1			T17	4		T18	6		T55	12
values[6]	3905	1			T12	22		T16	20		T45	40
values[7]	4167	1			T9	6		T45	20		T183	8

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4275	1			T9	6		T56	8		T45	20
values[1]	3557	1			T18	6		T207	24		T60	20
values[2]	4090	1			T16	20		T62	40		T60	20
values[3]	3972	1			T12	22		T45	60		T62	20
values[4]	4098	1			T10	80		T16	20		T45	20
values[5]	3994	1			T96	12		T58	86		T123	2
values[6]	4307	1			T6	8		T41	188		T55	12
values[7]	3985	1			T17	4		T109	20		T183	8

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31495

1

T6

8

T9

6

T10

80

auto[1]

783

1

T16

1

T18

2

T45

5

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	503	1			T49	61		T176	18		T217	19
auto[0]	values[0]	values[1]	570	1			T207	24		T213	75		T49	55
auto[0]	values[0]	values[2]	562	1			T295	18		T176	36		T39	25
auto[0]	values[0]	values[3]	688	1			T45	20		T47	20		T213	36
auto[0]	values[0]	values[4]	557	1			T16	20		T185	20		T75	20
auto[0]	values[0]	values[5]	578	1			T203	8		T60	20		T185	33
auto[0]	values[0]	values[6]	696	1			T41	188		T47	18		T213	32
auto[0]	values[0]	values[7]	443	1			T265	4		T262	2		T47	18
auto[0]	values[1]	values[0]	497	1			T64	25		T47	22		T185	41
auto[0]	values[1]	values[1]	511	1			T60	18		T248	12		T177	76
auto[0]	values[1]	values[2]	328	1			T47	23		T206	10		T296	6
auto[0]	values[1]	values[3]	525	1			T47	22		T222	24		T145	19
auto[0]	values[1]	values[4]	346	1			T238	20		T249	20		T215	20
auto[0]	values[1]	values[5]	449	1			T48	28		T220	14		T214	34
auto[0]	values[1]	values[6]	628	1			T138	20		T213	25		T39	66
auto[0]	values[1]	values[7]	365	1			T97	10		T99	20		T176	19
auto[0]	values[2]	values[0]	605	1			T95	24		T176	19		T217	18
auto[0]	values[2]	values[1]	280	1			T261	16		T210	20		T229	10
auto[0]	values[2]	values[2]	551	1			T71	20		T99	20		T204	2
auto[0]	values[2]	values[3]	533	1			T60	38		T64	29		T165	21
auto[0]	values[2]	values[4]	346	1			T10	80		T263	6		T211	16
auto[0]	values[2]	values[5]	312	1			T60	20		T99	39		T68	20
auto[0]	values[2]	values[6]	579	1			T6	8		T188	14		T64	21
auto[0]	values[2]	values[7]	426	1			T245	8		T64	29		T213	37
auto[0]	values[3]	values[0]	720	1			T56	8		T45	18		T57	14
auto[0]	values[3]	values[1]	545	1			T138	30		T48	20		T297	18
auto[0]	values[3]	values[2]	430	1			T185	20		T236	16		T71	20
auto[0]	values[3]	values[3]	310	1			T185	66		T213	18		T217	19
auto[0]	values[3]	values[4]	381	1			T244	8		T294	10		T254	2
auto[0]	values[3]	values[5]	332	1			T58	56		T176	20		T298	4
auto[0]	values[3]	values[6]	260	1			T100	22		T62	18		T185	20
auto[0]	values[3]	values[7]	349	1			T228	34		T218	58		T219	21
auto[0]	values[4]	values[0]	285	1			T299	10		T73	20		T300	6
auto[0]	values[4]	values[1]	383	1			T253	19		T256	20		T288	62
auto[0]	values[4]	values[2]	558	1			T47	20		T185	20		T221	8
auto[0]	values[4]	values[3]	580	1			T280	6		T74	6		T176	19
auto[0]	values[4]	values[4]	928	1			T62	20		T287	20		T210	20
auto[0]	values[4]	values[5]	561	1			T96	12		T213	20		T39	20
auto[0]	values[4]	values[6]	581	1			T64	20		T48	19		T49	37
auto[0]	values[4]	values[7]	452	1			T109	20		T60	19		T213	20
auto[0]	values[5]	values[0]	660	1			T73	25		T177	24		T231	12
auto[0]	values[5]	values[1]	491	1			T18	4		T264	4		T49	20
auto[0]	values[5]	values[2]	353	1			T209	12		T208	31		T256	18
auto[0]	values[5]	values[3]	478	1			T45	20		T286	6		T213	30
auto[0]	values[5]	values[4]	378	1			T54	8		T291	10		T232	30
auto[0]	values[5]	values[5]	515	1			T60	17		T49	69		T301	14
auto[0]	values[5]	values[6]	544	1			T55	12		T49	47		T274	34
auto[0]	values[5]	values[7]	649	1			T17	4		T223	10		T73	36
auto[0]	values[6]	values[0]	358	1			T271	4		T212	12		T99	20
auto[0]	values[6]	values[1]	249	1			T47	20		T256	20		T302	2
auto[0]	values[6]	values[2]	569	1			T16	19		T60	18		T255	18
auto[0]	values[6]	values[3]	472	1			T12	22		T45	17		T62	20
auto[0]	values[6]	values[4]	450	1			T58	32		T39	16		T165	20
auto[0]	values[6]	values[5]	493	1			T189	12		T60	18		T185	17
auto[0]	values[6]	values[6]	554	1			T45	20		T252	2		T145	20
auto[0]	values[6]	values[7]	666	1			T111	18		T61	14		T60	19
auto[0]	values[7]	values[0]	535	1			T9	6		T58	20		T60	19
auto[0]	values[7]	values[1]	446	1			T138	21		T303	22		T208	24
auto[0]	values[7]	values[2]	656	1			T62	39		T227	22		T49	56
auto[0]	values[7]	values[3]	285	1			T176	59		T217	20		T214	24
auto[0]	values[7]	values[4]	607	1			T45	20		T273	2		T185	20
auto[0]	values[7]	values[5]	652	1			T58	29		T123	2		T184	16
auto[0]	values[7]	values[6]	370	1			T98	24		T49	35		T270	10
auto[0]	values[7]	values[7]	532	1			T183	8		T269	10		T49	53
auto[1]	values[0]	values[0]	13	1			T49	1		T176	2		T217	1
auto[1]	values[0]	values[1]	6	1			T249	2		T215	2		T304	1
auto[1]	values[0]	values[2]	11	1			T176	2		T288	1		T305	4
auto[1]	values[0]	values[3]	13	1			T213	1		T68	1		T253	3
auto[1]	values[0]	values[4]	20	1			T75	4		T238	3		T260	2
auto[1]	values[0]	values[5]	19	1			T185	3		T99	1		T224	1
auto[1]	values[0]	values[6]	12	1			T47	2		T73	1		T306	2
auto[1]	values[0]	values[7]	18	1			T47	2		T185	2		T215	2
auto[1]	values[1]	values[0]	9	1			T64	1		T47	3		T177	2
auto[1]	values[1]	values[1]	8	1			T60	2		T177	1		T168	3
auto[1]	values[1]	values[2]	9	1			T47	1		T307	2		T285	2
auto[1]	values[1]	values[3]	12	1			T145	1		T214	2		T235	3
auto[1]	values[1]	values[4]	5	1			T40	1		T308	1		T309	1
auto[1]	values[1]	values[5]	11	1			T48	2		T220	2		T214	1
auto[1]	values[1]	values[6]	9	1			T256	1		T218	3		T235	1
auto[1]	values[1]	values[7]	12	1			T176	1		T68	3		T249	1
auto[1]	values[2]	values[0]	21	1			T176	1		T217	2		T260	2
auto[1]	values[2]	values[1]	8	1			T310	4		T218	2		T305	1
auto[1]	values[2]	values[2]	9	1			T311	2		T312	2		T216	1
auto[1]	values[2]	values[3]	14	1			T60	2		T64	2		T313	4
auto[1]	values[2]	values[4]	3	1			T39	1		T314	1		T315	1
auto[1]	values[2]	values[5]	10	1			T99	1		T230	1		T87	3
auto[1]	values[2]	values[6]	9	1			T64	1		T99	2		T224	1
auto[1]	values[2]	values[7]	15	1			T64	2		T213	2		T99	2
auto[1]	values[3]	values[0]	26	1			T45	2		T185	4		T68	1
auto[1]	values[3]	values[1]	13	1			T138	2		T48	2		T281	2
auto[1]	values[3]	values[2]	10	1			T215	3		T235	1		T316	3
auto[1]	values[3]	values[3]	9	1			T185	1		T213	2		T217	1
auto[1]	values[3]	values[4]	13	1			T230	1		T317	2		T318	2
auto[1]	values[3]	values[5]	5	1			T39	1		T319	1		T320	3
auto[1]	values[3]	values[6]	12	1			T62	2		T71	1		T39	2
auto[1]	values[3]	values[7]	4	1			T218	3		T321	1		-	-
auto[1]	values[4]	values[0]	7	1			T73	3		T246	2		T219	1
auto[1]	values[4]	values[1]	14	1			T253	1		T219	2		T317	1
auto[1]	values[4]	values[2]	12	1			T138	2		T165	3		T87	3
auto[1]	values[4]	values[3]	20	1			T280	2		T176	1		T230	1
auto[1]	values[4]	values[4]	29	1			T253	1		T293	3		T312	4
auto[1]	values[4]	values[5]	11	1			T256	1		T219	4		T322	1
auto[1]	values[4]	values[6]	16	1			T48	1		T49	1		T323	2
auto[1]	values[4]	values[7]	16	1			T60	1		T224	1		T281	2
auto[1]	values[5]	values[0]	13	1			T73	2		T177	2		T258	1
auto[1]	values[5]	values[1]	20	1			T18	2		T182	4		T324	4
auto[1]	values[5]	values[2]	4	1			T256	2		T325	2		-	-
auto[1]	values[5]	values[3]	12	1			T213	1		T217	1		T87	1
auto[1]	values[5]	values[4]	12	1			T230	2		T218	2		T305	1
auto[1]	values[5]	values[5]	16	1			T60	3		T49	1		T260	1
auto[1]	values[5]	values[6]	20	1			T49	3		T230	2		T326	5
auto[1]	values[5]	values[7]	15	1			T39	2		T232	2		T293	2
auto[1]	values[6]	values[0]	5	1			T39	1		T258	1		T327	1
auto[1]	values[6]	values[1]	2	1			T328	1		T305	1		-	-
auto[1]	values[6]	values[2]	19	1			T16	1		T60	2		T258	1
auto[1]	values[6]	values[3]	17	1			T45	3		T99	1		T228	1
auto[1]	values[6]	values[4]	17	1			T39	4		T165	3		T230	1
auto[1]	values[6]	values[5]	13	1			T60	2		T185	3		T304	2
auto[1]	values[6]	values[6]	8	1			T49	1		T233	1		T215	1
auto[1]	values[6]	values[7]	13	1			T61	2		T60	1		T232	1
auto[1]	values[7]	values[0]	18	1			T60	1		T241	6		T87	2
auto[1]	values[7]	values[1]	11	1			T138	1		T39	1		T249	2
auto[1]	values[7]	values[2]	9	1			T62	1		T238	1		T219	1
auto[1]	values[7]	values[3]	4	1			T214	2		T285	2		-	-
auto[1]	values[7]	values[4]	6	1			T48	1		T253	1		T258	1
auto[1]	values[7]	values[5]	17	1			T58	1		T64	2		T208	1
auto[1]	values[7]	values[6]	9	1			T49	2		T217	2		T249	1
auto[1]	values[7]	values[7]	10	1			T63	2		T49	1		T208	1