Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	828	1			T20	11		T23	10		T34	11
all_values[1]	828	1			T20	11		T23	10		T34	11
all_values[2]	828	1			T20	11		T23	10		T34	11
all_values[3]	828	1			T20	11		T23	10		T34	11
all_values[4]	828	1			T20	11		T23	10		T34	11
all_values[5]	828	1			T20	11		T23	10		T34	11
all_values[6]	828	1			T20	11		T23	10		T34	11
all_values[7]	828	1			T20	11		T23	10		T34	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3537

1

T20

48

T23

37

T34

50

auto[1]

3087

1

T20

40

T23

43

T34

38

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2749

1

T20

39

T23

27

T34

37

auto[1]

3875

1

T20

49

T23

53

T34

51

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3801

1

T20

50

T23

43

T34

52

auto[1]

2823

1

T20

38

T23

37

T34

36

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	175	1			T20	4		T23	2		T34	3
all_values[0]	auto[0]	auto[0]	auto[1]	75	1			T23	1		T34	1		T35	2
all_values[0]	auto[0]	auto[1]	auto[0]	151	1			T20	3		T23	1		T34	1
all_values[0]	auto[0]	auto[1]	auto[1]	90	1			T23	1		T34	2		T35	6
all_values[0]	auto[1]	auto[0]	auto[1]	172	1			T20	3		T23	2		T34	2
all_values[0]	auto[1]	auto[1]	auto[1]	165	1			T20	1		T23	3		T34	2
all_values[1]	auto[0]	auto[0]	auto[0]	175	1			T20	4		T23	1		T34	3
all_values[1]	auto[0]	auto[0]	auto[1]	69	1			T20	1		T23	1		T34	1
all_values[1]	auto[0]	auto[1]	auto[0]	165	1			T20	3		T23	3		T34	1
all_values[1]	auto[0]	auto[1]	auto[1]	64	1			T20	1		T39	1		T87	1
all_values[1]	auto[1]	auto[0]	auto[1]	198	1			T20	1		T23	2		T34	2
all_values[1]	auto[1]	auto[1]	auto[1]	157	1			T20	1		T23	3		T34	4
all_values[2]	auto[0]	auto[0]	auto[0]	173	1			T20	1		T34	5		T35	2
all_values[2]	auto[0]	auto[0]	auto[1]	70	1			T34	1		T35	2		T164	1
all_values[2]	auto[0]	auto[1]	auto[0]	150	1			T20	3		T23	3		T34	2
all_values[2]	auto[0]	auto[1]	auto[1]	84	1			T20	2		T23	3		T35	2
all_values[2]	auto[1]	auto[0]	auto[1]	196	1			T20	4		T23	3		T34	2
all_values[2]	auto[1]	auto[1]	auto[1]	155	1			T20	1		T23	1		T34	1
all_values[3]	auto[0]	auto[0]	auto[0]	172	1			T20	1		T34	3		T35	2
all_values[3]	auto[0]	auto[0]	auto[1]	77	1			T20	1		T23	2		T34	1
all_values[3]	auto[0]	auto[1]	auto[0]	143	1			T20	2		T23	2		T34	2
all_values[3]	auto[0]	auto[1]	auto[1]	67	1			T20	1		T23	2		T34	1
all_values[3]	auto[1]	auto[0]	auto[1]	207	1			T20	3		T23	1		T34	3
all_values[3]	auto[1]	auto[1]	auto[1]	162	1			T20	3		T23	3		T34	1
all_values[4]	auto[0]	auto[0]	auto[0]	160	1			T20	6		T23	2		T35	7
all_values[4]	auto[0]	auto[0]	auto[1]	75	1			T34	2		T164	4		T165	1
all_values[4]	auto[0]	auto[1]	auto[0]	146	1			T23	2		T35	3		T164	2
all_values[4]	auto[0]	auto[1]	auto[1]	83	1			T34	1		T35	1		T164	4
all_values[4]	auto[1]	auto[0]	auto[1]	177	1			T20	1		T23	1		T34	2
all_values[4]	auto[1]	auto[1]	auto[1]	187	1			T20	4		T23	5		T34	6
all_values[5]	auto[0]	auto[0]	auto[0]	249	1			T20	3		T23	3		T34	5
all_values[5]	auto[0]	auto[1]	auto[0]	220	1			T20	2		T23	1		T34	5
all_values[5]	auto[1]	auto[0]	auto[1]	202	1			T20	4		T23	5		T35	2
all_values[5]	auto[1]	auto[1]	auto[1]	157	1			T20	2		T23	1		T34	1
all_values[6]	auto[0]	auto[0]	auto[0]	201	1			T20	3		T23	2		T34	4
all_values[6]	auto[0]	auto[0]	auto[1]	72	1			T20	2		T23	1		T35	1
all_values[6]	auto[0]	auto[1]	auto[0]	149	1			T20	1		T23	2		T34	1
all_values[6]	auto[0]	auto[1]	auto[1]	71	1			T20	2		T23	1		T35	1
all_values[6]	auto[1]	auto[0]	auto[1]	178	1			T20	2		T23	3		T34	5
all_values[6]	auto[1]	auto[1]	auto[1]	157	1			T20	1		T23	1		T34	1
all_values[7]	auto[0]	auto[0]	auto[0]	185	1			T20	1		T23	2		T34	2
all_values[7]	auto[0]	auto[0]	auto[1]	77	1			T23	1		T34	1		T35	1
all_values[7]	auto[0]	auto[1]	auto[0]	135	1			T20	2		T23	1		T35	3
all_values[7]	auto[0]	auto[1]	auto[1]	78	1			T20	1		T23	3		T34	4
all_values[7]	auto[1]	auto[0]	auto[1]	202	1			T20	3		T23	2		T34	2
all_values[7]	auto[1]	auto[1]	auto[1]	151	1			T20	4		T23	1		T34	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal