Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1848

1

T4

2

T7

5

T26

1

auto[1]

1914

1

T4

2

T7

1

T26

8

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2180

1

T29

10

T31

22

T44

1

auto[1]

1582

1

T4

4

T7

6

T26

9

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2974

1

T4

4

T7

6

T26

9

auto[1]

788

1

T31

10

T44

1

T42

4

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	730	1			T26	3		T28	3		T29	3
valid[1]	760	1			T7	1		T26	2		T28	7
valid[2]	766	1			T4	4		T26	1		T28	5
valid[3]	795	1			T7	4		T26	1		T28	3
valid[4]	711	1			T7	1		T26	2		T28	4

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	137	1			T29	1		T31	2		T46	4
auto[0]	auto[0]	valid[0]	auto[1]	136	1			T28	1		T30	1		T31	1
auto[0]	auto[0]	valid[1]	auto[0]	141	1			T31	2		T42	1		T46	3
auto[0]	auto[0]	valid[1]	auto[1]	163	1			T7	1		T26	1		T28	3
auto[0]	auto[0]	valid[2]	auto[0]	142	1			T29	3		T31	2		T46	1
auto[0]	auto[0]	valid[2]	auto[1]	135	1			T4	2		T28	4		T30	1
auto[0]	auto[0]	valid[3]	auto[0]	149	1			T29	1		T42	3		T46	2
auto[0]	auto[0]	valid[3]	auto[1]	152	1			T7	3		T28	2		T31	2
auto[0]	auto[0]	valid[4]	auto[0]	132	1			T29	1		T31	1		T42	2
auto[0]	auto[0]	valid[4]	auto[1]	144	1			T7	1		T92	1		T93	3
auto[0]	auto[1]	valid[0]	auto[0]	147	1			T29	2		T31	1		T46	2
auto[0]	auto[1]	valid[0]	auto[1]	165	1			T26	3		T28	2		T31	1
auto[0]	auto[1]	valid[1]	auto[0]	146	1			T31	1		T42	2		T46	1
auto[0]	auto[1]	valid[1]	auto[1]	164	1			T26	1		T28	4		T30	2
auto[0]	auto[1]	valid[2]	auto[0]	140	1			T29	1		T42	1		T46	1
auto[0]	auto[1]	valid[2]	auto[1]	182	1			T4	2		T26	1		T28	1
auto[0]	auto[1]	valid[3]	auto[0]	133	1			T42	1		T46	1		T43	2
auto[0]	auto[1]	valid[3]	auto[1]	173	1			T7	1		T26	1		T28	1
auto[0]	auto[1]	valid[4]	auto[0]	125	1			T29	1		T31	3		T46	1
auto[0]	auto[1]	valid[4]	auto[1]	168	1			T26	2		T28	4		T30	1
auto[1]	auto[0]	valid[0]	auto[0]	79	1			T31	2		T46	1		T65	1
auto[1]	auto[0]	valid[1]	auto[0]	74	1			T46	1		T339	1		T146	1
auto[1]	auto[0]	valid[2]	auto[0]	85	1			T47	1		T137	1		T339	1
auto[1]	auto[0]	valid[3]	auto[0]	102	1			T42	2		T65	1		T64	1
auto[1]	auto[0]	valid[4]	auto[0]	77	1			T31	2		T44	1		T42	1
auto[1]	auto[1]	valid[0]	auto[0]	66	1			T42	1		T46	2		T349	1
auto[1]	auto[1]	valid[1]	auto[0]	72	1			T51	2		T337	2		T48	1
auto[1]	auto[1]	valid[2]	auto[0]	82	1			T31	2		T46	3		T51	1
auto[1]	auto[1]	valid[3]	auto[0]	86	1			T31	3		T46	1		T43	2
auto[1]	auto[1]	valid[4]	auto[0]	65	1			T31	1		T65	2		T337	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal