Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

54752

1

T5

8

T27

4

T29

304

auto[1]

16377

1

T4

4

T7

132

T26

9

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51114

1

T4

4

T5

4

T7

132

auto[1]

20015

1

T5

4

T27

2

T29

97

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	36766	1			T4	4		T5	7		T7	74
others[1]	6045	1			T5	1		T7	12		T28	27
others[2]	6008	1			T7	4		T28	24		T29	28
others[3]	6760	1			T7	15		T27	1		T28	36
interest[1]	3860	1			T7	8		T28	11		T29	16
interest[4]	24144	1			T4	4		T5	5		T7	46
interest[64]	11690	1			T7	19		T27	1		T28	64

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	17927	1			T5	4		T27	1		T29	95
auto[0]	auto[0]	others[1]	2988	1			T29	22		T31	14		T42	18
auto[0]	auto[0]	others[2]	2949	1			T29	20		T31	14		T44	1
auto[0]	auto[0]	others[3]	3339	1			T29	22		T31	21		T44	1
auto[0]	auto[0]	interest[1]	1870	1			T29	9		T31	14		T42	13
auto[0]	auto[0]	interest[4]	11733	1			T5	3		T27	1		T29	57
auto[0]	auto[0]	interest[64]	5664	1			T27	1		T29	39		T31	46
auto[0]	auto[1]	others[0]	8537	1			T4	4		T7	74		T26	9
auto[0]	auto[1]	others[1]	1351	1			T7	12		T28	27		T30	2
auto[0]	auto[1]	others[2]	1370	1			T7	4		T28	24		T30	5
auto[0]	auto[1]	others[3]	1525	1			T7	15		T28	36		T30	1
auto[0]	auto[1]	interest[1]	897	1			T7	8		T28	11		T30	2
auto[0]	auto[1]	interest[4]	5698	1			T4	4		T7	46		T26	9
auto[0]	auto[1]	interest[64]	2697	1			T7	19		T28	64		T30	6
auto[1]	auto[0]	others[0]	10302	1			T5	3		T27	1		T29	50
auto[1]	auto[0]	others[1]	1706	1			T5	1		T29	7		T31	12
auto[1]	auto[0]	others[2]	1689	1			T29	8		T31	12		T42	9
auto[1]	auto[0]	others[3]	1896	1			T27	1		T29	10		T31	20
auto[1]	auto[0]	interest[1]	1093	1			T29	7		T31	14		T42	5
auto[1]	auto[0]	interest[4]	6713	1			T5	2		T29	26		T31	61
auto[1]	auto[0]	interest[64]	3329	1			T29	15		T31	31		T44	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal