Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2455223	1			T1	1		T2	1		T3	1
all_values[1]	2455223	1			T1	1		T2	1		T3	1
all_values[2]	2455223	1			T1	1		T2	1		T3	1
all_values[3]	2455223	1			T1	1		T2	1		T3	1
all_values[4]	2455223	1			T1	1		T2	1		T3	1
all_values[5]	2455223	1			T1	1		T2	1		T3	1
all_values[6]	2455223	1			T1	1		T2	1		T3	1
all_values[7]	2455223	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19118933

1

T1

8

T2

8

T3

8

auto[1]

522851

1

T8

49

T26

36

T35

82

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19618846

1

T1

8

T2

8

T3

8

auto[1]

22938

1

T8

31

T26

18

T53

42

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2312108	1			T1	1		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	10633	1			T8	5		T26	2		T53	16
all_values[0]	auto[1]	auto[0]	131973	1			T8	2		T26	4		T35	6
all_values[0]	auto[1]	auto[1]	509	1			T8	2		T26	1		T35	3
all_values[1]	auto[0]	auto[0]	2428469	1			T1	1		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	6849	1			T8	2		T26	1		T53	13
all_values[1]	auto[1]	auto[0]	19531	1			T8	3		T26	6		T35	8
all_values[1]	auto[1]	auto[1]	374	1			T8	3		T26	1		T35	6
all_values[2]	auto[0]	auto[0]	2348060	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	2277	1			T53	13		T35	2		T36	3
all_values[2]	auto[1]	auto[0]	104625	1			T8	4		T26	2		T35	8
all_values[2]	auto[1]	auto[1]	261	1			T8	2		T26	3		T35	3
all_values[3]	auto[0]	auto[0]	2388593	1			T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	214	1			T8	3		T26	1		T35	2
all_values[3]	auto[1]	auto[0]	66217	1			T8	2		T26	1		T35	12
all_values[3]	auto[1]	auto[1]	199	1			T8	2		T26	3		T35	2
all_values[4]	auto[0]	auto[0]	2433991	1			T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	209	1			T8	1		T26	1		T35	3
all_values[4]	auto[1]	auto[0]	20797	1			T8	6		T26	5		T35	9
all_values[4]	auto[1]	auto[1]	226	1			T8	3		T35	3		T36	4
all_values[5]	auto[0]	auto[0]	2384334	1			T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	203	1			T8	1		T35	3		T37	4
all_values[5]	auto[1]	auto[0]	70510	1			T8	7		T26	2		T35	8
all_values[5]	auto[1]	auto[1]	176	1			T8	2		T26	2		T35	3
all_values[6]	auto[0]	auto[0]	2364158	1			T1	1		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	194	1			T8	1		T35	2		T37	4
all_values[6]	auto[1]	auto[0]	90650	1			T8	3		T26	2		T35	1
all_values[6]	auto[1]	auto[1]	221	1			T8	2		T26	2		T35	5
all_values[7]	auto[0]	auto[0]	2438438	1			T1	1		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	203	1			T8	2		T26	1		T35	7
all_values[7]	auto[1]	auto[0]	16392	1			T8	6		T26	2		T35	5
all_values[7]	auto[1]	auto[1]	190	1			T36	3		T37	4		T203	5