Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.03 98.38 93.99 98.62 89.36 97.19 95.57 99.11


Total tests in report: 1131
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
57.50 57.50 88.80 88.80 76.91 76.91 78.74 78.74 0.00 0.00 84.76 84.76 65.01 65.01 8.27 8.27 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_upload.3517095133
68.25 10.76 91.26 2.47 81.49 4.59 78.84 0.10 46.67 46.67 87.93 3.17 71.92 6.92 19.65 11.39 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.2243455198
76.08 7.83 95.17 3.91 84.73 3.23 83.76 4.92 73.33 26.67 92.65 4.72 79.25 7.33 23.66 4.01 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_mailbox.1554316974
80.62 4.54 97.30 2.13 88.57 3.84 85.33 1.57 82.22 8.89 95.58 2.93 84.65 5.39 30.69 7.03 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_all.833899218
82.99 2.36 97.72 0.42 89.73 1.16 87.60 2.26 84.44 2.22 96.09 0.51 84.92 0.28 40.40 9.70 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_stress_all.3751890145
84.97 1.98 97.85 0.13 90.00 0.27 87.60 0.00 91.11 6.67 96.34 0.25 84.92 0.00 46.93 6.53 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_all.1736137550
86.80 1.83 97.85 0.00 90.01 0.01 87.60 0.00 91.11 0.00 96.34 0.00 84.92 0.00 59.75 12.82 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.2059375951
88.39 1.59 97.85 0.00 90.18 0.16 88.39 0.79 91.11 0.00 96.38 0.03 93.36 8.44 61.44 1.68 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3313208026
89.39 1.00 97.91 0.06 90.24 0.06 88.39 0.00 93.33 2.22 96.46 0.08 93.36 0.00 66.04 4.60 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_all.1405946881
90.27 0.88 97.91 0.00 90.24 0.00 88.39 0.00 93.33 0.00 96.46 0.00 93.36 0.00 72.23 6.19 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.3438002130
90.96 0.69 98.12 0.21 91.02 0.78 90.16 1.77 93.33 0.00 96.89 0.42 94.05 0.69 73.17 0.94 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode.2767045241
91.64 0.68 98.14 0.02 91.02 0.00 94.88 4.72 93.33 0.00 96.89 0.00 94.05 0.00 73.17 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_ram_cfg.812937053
92.29 0.65 98.14 0.00 92.49 1.47 94.88 0.00 93.33 0.00 96.89 0.00 94.05 0.00 76.24 3.07 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_all.1661297508
92.77 0.49 98.15 0.01 92.53 0.04 97.83 2.95 93.33 0.00 96.90 0.02 94.19 0.14 76.49 0.25 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_sec_cm.2178357665
93.18 0.40 98.15 0.00 92.53 0.00 97.83 0.00 93.33 0.00 96.90 0.00 94.19 0.00 79.31 2.82 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_stress_all.2326625705
93.53 0.35 98.18 0.03 92.56 0.04 97.83 0.00 93.33 0.00 96.97 0.07 94.47 0.28 81.34 2.03 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_stress_all.1173557257
93.79 0.27 98.18 0.00 92.56 0.00 97.83 0.00 93.33 0.00 96.97 0.00 94.47 0.00 83.22 1.88 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm_min_idle.3993152290
94.05 0.25 98.26 0.08 92.77 0.21 98.03 0.20 93.33 0.00 97.07 0.10 94.74 0.28 84.11 0.89 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.4133610143
94.28 0.24 98.32 0.06 92.90 0.12 98.43 0.39 93.33 0.00 97.12 0.05 94.74 0.00 85.15 1.04 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_upload.763980545
94.50 0.21 98.32 0.00 92.90 0.00 98.43 0.00 93.33 0.00 97.12 0.00 94.74 0.00 86.63 1.49 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm_min_idle.329286619
94.69 0.20 98.32 0.00 92.90 0.00 98.43 0.00 93.33 0.00 97.12 0.00 94.74 0.00 88.02 1.39 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.2019934028
94.87 0.18 98.32 0.00 92.91 0.01 98.43 0.00 93.33 0.00 97.12 0.00 94.74 0.00 89.26 1.24 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_mode_ignore_cmds.794050126
95.03 0.16 98.32 0.01 92.96 0.05 98.43 0.00 93.33 0.00 97.14 0.02 94.74 0.00 90.30 1.04 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.2249930676
95.19 0.16 98.32 0.00 92.97 0.01 98.43 0.00 93.33 0.00 97.14 0.00 94.74 0.00 91.39 1.09 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.306772871
95.34 0.15 98.32 0.00 92.97 0.00 98.43 0.00 93.33 0.00 97.14 0.00 94.74 0.00 92.43 1.04 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_mode_ignore_cmds.300383915
95.48 0.14 98.32 0.00 93.76 0.78 98.43 0.00 93.33 0.00 97.14 0.00 94.74 0.00 92.62 0.20 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.1316754190
95.60 0.12 98.32 0.00 93.76 0.00 98.43 0.00 93.33 0.00 97.14 0.00 95.57 0.83 92.62 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.1915466968
95.70 0.10 98.32 0.00 93.76 0.00 98.43 0.00 93.33 0.00 97.14 0.00 95.57 0.00 93.32 0.69 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_all.1742354326
95.78 0.08 98.32 0.00 93.76 0.00 98.43 0.00 93.33 0.00 97.14 0.00 95.57 0.00 93.91 0.59 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_and_tpm_min_idle.2045600797
95.87 0.08 98.32 0.00 93.76 0.00 98.43 0.00 93.33 0.00 97.14 0.00 95.57 0.00 94.50 0.59 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.2514936309
95.92 0.06 98.32 0.00 93.76 0.00 98.43 0.00 93.33 0.00 97.14 0.00 95.57 0.00 94.90 0.40 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.1328208079
95.97 0.05 98.32 0.00 93.76 0.00 98.43 0.00 93.33 0.00 97.14 0.00 95.57 0.00 95.25 0.35 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.1532269479
96.02 0.05 98.32 0.00 93.76 0.00 98.43 0.00 93.33 0.00 97.14 0.00 95.57 0.00 95.59 0.35 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_all.2706475778
96.06 0.04 98.32 0.00 93.76 0.00 98.43 0.00 93.33 0.00 97.14 0.00 95.57 0.00 95.89 0.30 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_all.2331695101
96.11 0.04 98.32 0.00 93.76 0.00 98.43 0.00 93.33 0.00 97.14 0.00 95.57 0.00 96.19 0.30 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_all.1381836294
96.14 0.04 98.35 0.03 93.79 0.04 98.62 0.20 93.33 0.00 97.14 0.00 95.57 0.00 96.19 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_alert_test.1058119798
96.18 0.04 98.35 0.00 93.79 0.00 98.62 0.00 93.33 0.00 97.14 0.00 95.57 0.00 96.44 0.25 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.2845527380
96.21 0.04 98.35 0.00 93.79 0.00 98.62 0.00 93.33 0.00 97.14 0.00 95.57 0.00 96.68 0.25 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm_min_idle.806879276
96.25 0.03 98.36 0.01 93.79 0.00 98.62 0.00 93.33 0.00 97.16 0.02 95.57 0.00 96.88 0.20 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.3796253443
96.27 0.03 98.36 0.00 93.79 0.00 98.62 0.00 93.33 0.00 97.16 0.00 95.57 0.00 97.08 0.20 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.3337439283
96.30 0.03 98.36 0.00 93.79 0.00 98.62 0.00 93.33 0.00 97.16 0.00 95.57 0.00 97.28 0.20 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode.2451871268
96.33 0.03 98.36 0.00 93.79 0.00 98.62 0.00 93.33 0.00 97.16 0.00 95.57 0.00 97.48 0.20 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_upload.1820761616
96.36 0.03 98.36 0.00 93.79 0.00 98.62 0.00 93.33 0.00 97.16 0.00 95.57 0.00 97.67 0.20 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.2343831892
96.38 0.02 98.36 0.00 93.79 0.00 98.62 0.00 93.33 0.00 97.16 0.00 95.57 0.00 97.82 0.15 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.3411370573
96.40 0.02 98.36 0.00 93.87 0.07 98.62 0.00 93.33 0.00 97.16 0.00 95.57 0.00 97.87 0.05 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.560879457
96.41 0.01 98.36 0.00 93.87 0.00 98.62 0.00 93.33 0.00 97.16 0.00 95.57 0.00 97.97 0.10 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.3873356022
96.43 0.01 98.36 0.00 93.87 0.00 98.62 0.00 93.33 0.00 97.16 0.00 95.57 0.00 98.07 0.10 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.191011434
96.44 0.01 98.36 0.00 93.87 0.00 98.62 0.00 93.33 0.00 97.16 0.00 95.57 0.00 98.17 0.10 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_cfg_cmd.3721421719
96.45 0.01 98.36 0.00 93.87 0.00 98.62 0.00 93.33 0.00 97.16 0.00 95.57 0.00 98.27 0.10 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_and_tpm_min_idle.561699383
96.47 0.01 98.36 0.00 93.87 0.00 98.62 0.00 93.33 0.00 97.16 0.00 95.57 0.00 98.37 0.10 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_mode_ignore_cmds.664601675
96.48 0.01 98.36 0.00 93.87 0.00 98.62 0.00 93.33 0.00 97.16 0.00 95.57 0.00 98.47 0.10 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_intercept.510697928
96.50 0.01 98.36 0.00 93.89 0.02 98.62 0.00 93.33 0.00 97.17 0.02 95.57 0.00 98.51 0.05 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_cfg_cmd.3093652706
96.50 0.01 98.36 0.00 93.91 0.01 98.62 0.00 93.33 0.00 97.17 0.00 95.57 0.00 98.56 0.05 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.3949116417
96.51 0.01 98.36 0.00 93.91 0.00 98.62 0.00 93.33 0.00 97.17 0.00 95.57 0.00 98.61 0.05 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.2948587533
96.52 0.01 98.36 0.00 93.91 0.00 98.62 0.00 93.33 0.00 97.17 0.00 95.57 0.00 98.66 0.05 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_cfg_cmd.1491862286
96.53 0.01 98.36 0.00 93.91 0.00 98.62 0.00 93.33 0.00 97.17 0.00 95.57 0.00 98.71 0.05 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_mailbox.3989657181
96.53 0.01 98.36 0.00 93.91 0.00 98.62 0.00 93.33 0.00 97.17 0.00 95.57 0.00 98.76 0.05 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_upload.3242923578
96.54 0.01 98.36 0.00 93.91 0.00 98.62 0.00 93.33 0.00 97.17 0.00 95.57 0.00 98.81 0.05 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.318049927
96.55 0.01 98.36 0.00 93.91 0.00 98.62 0.00 93.33 0.00 97.17 0.00 95.57 0.00 98.86 0.05 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode_ignore_cmds.3977489021
96.55 0.01 98.36 0.00 93.91 0.00 98.62 0.00 93.33 0.00 97.17 0.00 95.57 0.00 98.91 0.05 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode.459130519
96.56 0.01 98.36 0.00 93.91 0.00 98.62 0.00 93.33 0.00 97.17 0.00 95.57 0.00 98.96 0.05 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.2909474427
96.57 0.01 98.36 0.00 93.91 0.00 98.62 0.00 93.33 0.00 97.17 0.00 95.57 0.00 99.01 0.05 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_stress_all.2242498041
96.58 0.01 98.36 0.00 93.91 0.00 98.62 0.00 93.33 0.00 97.17 0.00 95.57 0.00 99.06 0.05 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_all.3955457030
96.58 0.01 98.36 0.00 93.91 0.00 98.62 0.00 93.33 0.00 97.17 0.00 95.57 0.00 99.11 0.05 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.3007971600
96.59 0.01 98.38 0.02 93.93 0.02 98.62 0.00 93.33 0.00 97.17 0.00 95.57 0.00 99.11 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_csb_read.1741752492
96.59 0.01 98.38 0.00 93.96 0.02 98.62 0.00 93.33 0.00 97.19 0.02 95.57 0.00 99.11 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_mode_ignore_cmds.812063061
96.60 0.01 98.38 0.00 93.98 0.02 98.62 0.00 93.33 0.00 97.19 0.00 95.57 0.00 99.11 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1555173361
96.60 0.01 98.38 0.00 93.99 0.01 98.62 0.00 93.33 0.00 97.19 0.00 95.57 0.00 99.11 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.326684180

Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.2087470803
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.4031010710
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1018966804
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.400517513
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.2833995282
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.1377673583
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3997137064
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.3633589193
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.2862707857
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/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_upload.210189919



Total test records in report: 1131
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_csb_read.1741752492 Sep 24 02:36:39 PM UTC 24 Sep 24 02:36:41 PM UTC 24 138190198 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_csb_read.342899598 Sep 24 02:37:31 PM UTC 24 Sep 24 02:37:33 PM UTC 24 36820056 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_ram_cfg.812937053 Sep 24 02:36:40 PM UTC 24 Sep 24 02:36:43 PM UTC 24 19521552 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.1478951093 Sep 24 02:36:41 PM UTC 24 Sep 24 02:36:43 PM UTC 24 33356148 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_rw.1062483287 Sep 24 02:36:42 PM UTC 24 Sep 24 02:36:44 PM UTC 24 175798788 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.863836446 Sep 24 02:36:42 PM UTC 24 Sep 24 02:36:45 PM UTC 24 32058197 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_alert_test.1058119798 Sep 24 02:36:43 PM UTC 24 Sep 24 02:36:46 PM UTC 24 16959608 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_stress_all.1565822432 Sep 24 02:36:43 PM UTC 24 Sep 24 02:36:46 PM UTC 24 417278187 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_sec_cm.2178357665 Sep 24 02:36:43 PM UTC 24 Sep 24 02:36:46 PM UTC 24 277060707 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_upload.3517095133 Sep 24 02:36:43 PM UTC 24 Sep 24 02:36:46 PM UTC 24 86823295 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_mailbox.1554316974 Sep 24 02:37:05 PM UTC 24 Sep 24 02:37:38 PM UTC 24 41603539887 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_csb_read.1159005272 Sep 24 02:36:44 PM UTC 24 Sep 24 02:36:46 PM UTC 24 51683394 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.3528369239 Sep 24 02:36:45 PM UTC 24 Sep 24 02:36:47 PM UTC 24 73793455 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_cfg_cmd.1429952117 Sep 24 02:36:43 PM UTC 24 Sep 24 02:36:47 PM UTC 24 126459344 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_mailbox.3363671610 Sep 24 02:36:42 PM UTC 24 Sep 24 02:36:48 PM UTC 24 152236954 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.3997887212 Sep 24 02:36:43 PM UTC 24 Sep 24 02:36:48 PM UTC 24 701959798 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_rw.1881279037 Sep 24 02:36:45 PM UTC 24 Sep 24 02:36:49 PM UTC 24 604109238 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.3253819907 Sep 24 02:36:42 PM UTC 24 Sep 24 02:36:49 PM UTC 24 715403900 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.4133610143 Sep 24 02:36:40 PM UTC 24 Sep 24 02:36:50 PM UTC 24 2477869989 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_sec_cm.3499812351 Sep 24 02:37:30 PM UTC 24 Sep 24 02:37:33 PM UTC 24 113974539 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode.2767045241 Sep 24 02:36:43 PM UTC 24 Sep 24 02:36:51 PM UTC 24 226801753 ps
T160 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_all.2092772785 Sep 24 02:36:48 PM UTC 24 Sep 24 02:36:51 PM UTC 24 34285066 ps
T104 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_alert_test.649033525 Sep 24 02:36:50 PM UTC 24 Sep 24 02:36:52 PM UTC 24 11377065 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_stress_all.4258343323 Sep 24 02:36:50 PM UTC 24 Sep 24 02:36:52 PM UTC 24 124177606 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_sec_cm.3352438826 Sep 24 02:36:50 PM UTC 24 Sep 24 02:36:53 PM UTC 24 280678447 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_mailbox.3989657181 Sep 24 02:36:46 PM UTC 24 Sep 24 02:36:53 PM UTC 24 1188005690 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode.3754790805 Sep 24 02:36:48 PM UTC 24 Sep 24 02:36:54 PM UTC 24 118060293 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.1605899940 Sep 24 02:36:48 PM UTC 24 Sep 24 02:36:54 PM UTC 24 86978299 ps
T146 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_csb_read.4020894921 Sep 24 02:36:52 PM UTC 24 Sep 24 02:36:54 PM UTC 24 72221483 ps
T121 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_all.3348953451 Sep 24 02:36:53 PM UTC 24 Sep 24 02:36:56 PM UTC 24 12056944 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.1629874219 Sep 24 02:36:53 PM UTC 24 Sep 24 02:36:56 PM UTC 24 46651840 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_rw.2524209039 Sep 24 02:36:53 PM UTC 24 Sep 24 02:36:57 PM UTC 24 160758917 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.486011383 Sep 24 02:36:46 PM UTC 24 Sep 24 02:36:57 PM UTC 24 708965773 ps
T136 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.272094363 Sep 24 02:36:46 PM UTC 24 Sep 24 02:36:57 PM UTC 24 6681327529 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.1730087724 Sep 24 02:36:44 PM UTC 24 Sep 24 02:36:59 PM UTC 24 4423291932 ps
T119 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_upload.2843918171 Sep 24 02:36:54 PM UTC 24 Sep 24 02:36:59 PM UTC 24 3089870610 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_cfg_cmd.1491862286 Sep 24 02:36:48 PM UTC 24 Sep 24 02:37:00 PM UTC 24 2450908976 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_intercept.2338919981 Sep 24 02:36:46 PM UTC 24 Sep 24 02:37:02 PM UTC 24 1521078697 ps
T120 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_cfg_cmd.255535157 Sep 24 02:36:55 PM UTC 24 Sep 24 02:37:02 PM UTC 24 2224506012 ps
T105 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_alert_test.1096585755 Sep 24 02:37:00 PM UTC 24 Sep 24 02:37:03 PM UTC 24 64570297 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_sec_cm.2265954525 Sep 24 02:37:00 PM UTC 24 Sep 24 02:37:03 PM UTC 24 85166839 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_upload.763980545 Sep 24 02:37:06 PM UTC 24 Sep 24 02:37:34 PM UTC 24 27371663292 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_all.833899218 Sep 24 02:36:45 PM UTC 24 Sep 24 02:37:04 PM UTC 24 3160611881 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_intercept.2358818134 Sep 24 02:36:42 PM UTC 24 Sep 24 02:37:04 PM UTC 24 2718451194 ps
T445 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_csb_read.860821509 Sep 24 02:37:02 PM UTC 24 Sep 24 02:37:04 PM UTC 24 16267864 ps
T99 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_mailbox.3390181174 Sep 24 02:36:54 PM UTC 24 Sep 24 02:37:05 PM UTC 24 2112900055 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_rw.1686326363 Sep 24 02:37:04 PM UTC 24 Sep 24 02:37:07 PM UTC 24 97209881 ps
T126 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.3692509189 Sep 24 02:37:04 PM UTC 24 Sep 24 02:37:07 PM UTC 24 382817097 ps
T101 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.3746775987 Sep 24 02:36:53 PM UTC 24 Sep 24 02:37:09 PM UTC 24 1337310324 ps
T102 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.2653358814 Sep 24 02:36:57 PM UTC 24 Sep 24 02:37:09 PM UTC 24 1710493989 ps
T103 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_intercept.3050772040 Sep 24 02:36:54 PM UTC 24 Sep 24 02:37:11 PM UTC 24 2333848065 ps
T122 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.3595529273 Sep 24 02:37:03 PM UTC 24 Sep 24 02:37:11 PM UTC 24 1632439151 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_all.1661297508 Sep 24 02:36:40 PM UTC 24 Sep 24 02:37:11 PM UTC 24 9295456937 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_cfg_cmd.1327560766 Sep 24 02:37:07 PM UTC 24 Sep 24 02:37:14 PM UTC 24 351342874 ps
T127 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.3682661104 Sep 24 02:36:53 PM UTC 24 Sep 24 02:37:14 PM UTC 24 3167308695 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.4094072899 Sep 24 02:36:54 PM UTC 24 Sep 24 02:37:14 PM UTC 24 34295806939 ps
T137 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_upload.3242923578 Sep 24 02:36:47 PM UTC 24 Sep 24 02:37:14 PM UTC 24 24598051113 ps
T215 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode.941676739 Sep 24 02:37:08 PM UTC 24 Sep 24 02:37:14 PM UTC 24 264783844 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.1967457581 Sep 24 02:37:05 PM UTC 24 Sep 24 02:37:17 PM UTC 24 1271749465 ps
T446 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_csb_read.4244331382 Sep 24 02:37:15 PM UTC 24 Sep 24 02:37:17 PM UTC 24 49426452 ps
T447 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_alert_test.342735647 Sep 24 02:37:15 PM UTC 24 Sep 24 02:37:18 PM UTC 24 20572902 ps
T128 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.2474577664 Sep 24 02:37:33 PM UTC 24 Sep 24 02:37:36 PM UTC 24 370898823 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_sec_cm.4075342498 Sep 24 02:37:15 PM UTC 24 Sep 24 02:37:18 PM UTC 24 223524239 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode.4250363709 Sep 24 02:36:56 PM UTC 24 Sep 24 02:37:21 PM UTC 24 2517517352 ps
T448 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.2266034320 Sep 24 02:37:19 PM UTC 24 Sep 24 02:37:21 PM UTC 24 298930123 ps
T145 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.2082501427 Sep 24 02:37:10 PM UTC 24 Sep 24 02:37:22 PM UTC 24 1251180325 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_rw.4199959074 Sep 24 02:37:19 PM UTC 24 Sep 24 02:37:22 PM UTC 24 228526041 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_all.3481147598 Sep 24 02:37:18 PM UTC 24 Sep 24 02:37:24 PM UTC 24 1797074876 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.2190118560 Sep 24 02:37:10 PM UTC 24 Sep 24 02:37:25 PM UTC 24 906507634 ps
T77 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_intercept.2870619208 Sep 24 02:37:05 PM UTC 24 Sep 24 02:37:26 PM UTC 24 3725540705 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_intercept.1991177886 Sep 24 02:37:22 PM UTC 24 Sep 24 02:37:27 PM UTC 24 71270070 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_upload.2453635407 Sep 24 02:37:22 PM UTC 24 Sep 24 02:37:28 PM UTC 24 960881747 ps
T79 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.3718200189 Sep 24 02:37:18 PM UTC 24 Sep 24 02:37:28 PM UTC 24 1725851389 ps
T96 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode.3256805907 Sep 24 02:37:24 PM UTC 24 Sep 24 02:37:30 PM UTC 24 42428244 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.1940166999 Sep 24 02:37:19 PM UTC 24 Sep 24 02:37:30 PM UTC 24 11074346414 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_all.2331695101 Sep 24 02:36:43 PM UTC 24 Sep 24 02:37:30 PM UTC 24 4193361073 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.3801142970 Sep 24 02:36:43 PM UTC 24 Sep 24 02:37:31 PM UTC 24 9540478162 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_cfg_cmd.3754893093 Sep 24 02:37:23 PM UTC 24 Sep 24 02:37:32 PM UTC 24 836842869 ps
T449 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_alert_test.2085959820 Sep 24 02:37:31 PM UTC 24 Sep 24 02:37:33 PM UTC 24 16772011 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.2243455198 Sep 24 02:36:58 PM UTC 24 Sep 24 02:37:33 PM UTC 24 3646869213 ps
T70 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.3513793833 Sep 24 02:37:19 PM UTC 24 Sep 24 02:37:36 PM UTC 24 15524334511 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.1636102667 Sep 24 02:37:05 PM UTC 24 Sep 24 02:37:37 PM UTC 24 7212506912 ps
T61 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.3336428363 Sep 24 02:36:48 PM UTC 24 Sep 24 02:37:38 PM UTC 24 23348549084 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_rw.2753416592 Sep 24 02:37:34 PM UTC 24 Sep 24 02:37:39 PM UTC 24 1598060530 ps
T72 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.3750384672 Sep 24 02:37:26 PM UTC 24 Sep 24 02:37:39 PM UTC 24 500899899 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.480012005 Sep 24 02:37:32 PM UTC 24 Sep 24 02:37:40 PM UTC 24 4514480541 ps
T74 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_mailbox.3363721157 Sep 24 02:37:35 PM UTC 24 Sep 24 02:37:41 PM UTC 24 773666024 ps
T75 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_upload.228324179 Sep 24 02:37:37 PM UTC 24 Sep 24 02:37:43 PM UTC 24 466747679 ps
T450 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_alert_test.449411336 Sep 24 02:37:41 PM UTC 24 Sep 24 02:37:43 PM UTC 24 13285566 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode.1789071166 Sep 24 02:37:38 PM UTC 24 Sep 24 02:37:43 PM UTC 24 466122350 ps
T451 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_csb_read.3909031938 Sep 24 02:37:41 PM UTC 24 Sep 24 02:37:44 PM UTC 24 24548154 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.3796253443 Sep 24 02:37:35 PM UTC 24 Sep 24 02:37:46 PM UTC 24 1721729632 ps
T452 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_cfg_cmd.924278226 Sep 24 02:38:38 PM UTC 24 Sep 24 02:38:43 PM UTC 24 307973221 ps
T453 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.896354728 Sep 24 02:37:45 PM UTC 24 Sep 24 02:37:47 PM UTC 24 31956030 ps
T454 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.3836634764 Sep 24 02:37:45 PM UTC 24 Sep 24 02:37:47 PM UTC 24 29431080 ps
T123 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_all.2412511818 Sep 24 02:37:03 PM UTC 24 Sep 24 02:37:48 PM UTC 24 2422713903 ps
T436 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_rw.4127745873 Sep 24 02:37:45 PM UTC 24 Sep 24 02:37:49 PM UTC 24 1045162281 ps
T135 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.609160767 Sep 24 02:37:34 PM UTC 24 Sep 24 02:37:52 PM UTC 24 7842267854 ps
T231 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_intercept.2321173563 Sep 24 02:37:35 PM UTC 24 Sep 24 02:37:52 PM UTC 24 1380613370 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.191011434 Sep 24 02:36:43 PM UTC 24 Sep 24 02:37:55 PM UTC 24 4571888159 ps
T228 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.110944941 Sep 24 02:37:47 PM UTC 24 Sep 24 02:37:55 PM UTC 24 691500537 ps
T259 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_cfg_cmd.1930478101 Sep 24 02:37:50 PM UTC 24 Sep 24 02:37:56 PM UTC 24 92745801 ps
T147 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_intercept.510697928 Sep 24 02:37:48 PM UTC 24 Sep 24 02:37:56 PM UTC 24 356360601 ps
T455 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_all.3587319587 Sep 24 02:37:56 PM UTC 24 Sep 24 02:37:58 PM UTC 24 19561607 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.2913134480 Sep 24 02:37:40 PM UTC 24 Sep 24 02:38:00 PM UTC 24 3721888002 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_stress_all.715571498 Sep 24 02:37:57 PM UTC 24 Sep 24 02:38:00 PM UTC 24 49024104 ps
T94 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_all.697536759 Sep 24 02:38:08 PM UTC 24 Sep 24 02:38:44 PM UTC 24 6234269106 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_stress_all.3751890145 Sep 24 02:37:29 PM UTC 24 Sep 24 02:38:00 PM UTC 24 2365292907 ps
T210 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_alert_test.3184420497 Sep 24 02:37:59 PM UTC 24 Sep 24 02:38:01 PM UTC 24 15288236 ps
T211 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_csb_read.2896595699 Sep 24 02:37:59 PM UTC 24 Sep 24 02:38:01 PM UTC 24 17616266 ps
T191 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.1909282902 Sep 24 02:37:53 PM UTC 24 Sep 24 02:38:02 PM UTC 24 991409183 ps
T125 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_all.4074051662 Sep 24 02:37:33 PM UTC 24 Sep 24 02:38:02 PM UTC 24 4665412628 ps
T129 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_cfg_cmd.2455633343 Sep 24 02:37:37 PM UTC 24 Sep 24 02:38:04 PM UTC 24 2302700930 ps
T212 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_all.436938268 Sep 24 02:38:02 PM UTC 24 Sep 24 02:38:04 PM UTC 24 14089655 ps
T213 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.3240624744 Sep 24 02:38:02 PM UTC 24 Sep 24 02:38:05 PM UTC 24 27525711 ps
T214 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_rw.3985340888 Sep 24 02:38:02 PM UTC 24 Sep 24 02:38:05 PM UTC 24 11907694 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.2677737791 Sep 24 02:37:29 PM UTC 24 Sep 24 02:38:05 PM UTC 24 1948564571 ps
T438 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_all.574919760 Sep 24 02:37:45 PM UTC 24 Sep 24 02:38:07 PM UTC 24 1580063684 ps
T229 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_mailbox.2469997043 Sep 24 02:37:48 PM UTC 24 Sep 24 02:38:07 PM UTC 24 463980403 ps
T456 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.3376859521 Sep 24 02:38:01 PM UTC 24 Sep 24 02:38:09 PM UTC 24 707274283 ps
T457 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_cfg_cmd.3885686442 Sep 24 02:38:05 PM UTC 24 Sep 24 02:38:09 PM UTC 24 27441358 ps
T242 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.1920302888 Sep 24 02:37:47 PM UTC 24 Sep 24 02:38:09 PM UTC 24 13977525220 ps
T230 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.1009472960 Sep 24 02:38:04 PM UTC 24 Sep 24 02:38:09 PM UTC 24 247414085 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.2476948851 Sep 24 02:37:38 PM UTC 24 Sep 24 02:38:10 PM UTC 24 14297042212 ps
T458 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode.1999465582 Sep 24 02:37:50 PM UTC 24 Sep 24 02:38:11 PM UTC 24 2598905934 ps
T192 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode.159884727 Sep 24 02:38:06 PM UTC 24 Sep 24 02:38:12 PM UTC 24 66457831 ps
T459 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.336196856 Sep 24 02:38:06 PM UTC 24 Sep 24 02:38:12 PM UTC 24 116834106 ps
T460 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_alert_test.2700704779 Sep 24 02:38:11 PM UTC 24 Sep 24 02:38:13 PM UTC 24 36603847 ps
T148 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_mailbox.543174166 Sep 24 02:38:16 PM UTC 24 Sep 24 02:38:45 PM UTC 24 1983873728 ps
T461 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_csb_read.1542305091 Sep 24 02:38:11 PM UTC 24 Sep 24 02:38:13 PM UTC 24 20990470 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_mailbox.975082509 Sep 24 02:38:04 PM UTC 24 Sep 24 02:38:15 PM UTC 24 416806029 ps
T462 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.1175811038 Sep 24 02:38:13 PM UTC 24 Sep 24 02:38:16 PM UTC 24 89696214 ps
T109 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_upload.949977477 Sep 24 02:38:05 PM UTC 24 Sep 24 02:38:17 PM UTC 24 1692790635 ps
T463 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_rw.2266333683 Sep 24 02:38:14 PM UTC 24 Sep 24 02:38:18 PM UTC 24 123214651 ps
T395 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.3161741761 Sep 24 02:38:02 PM UTC 24 Sep 24 02:38:18 PM UTC 24 8026506283 ps
T110 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_upload.1820761616 Sep 24 02:37:48 PM UTC 24 Sep 24 02:38:20 PM UTC 24 6759576051 ps
T435 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_all.2460296855 Sep 24 02:38:13 PM UTC 24 Sep 24 02:38:23 PM UTC 24 685852441 ps
T142 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_intercept.1889586251 Sep 24 02:38:04 PM UTC 24 Sep 24 02:38:23 PM UTC 24 1472413105 ps
T239 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_upload.3233463969 Sep 24 02:38:18 PM UTC 24 Sep 24 02:38:23 PM UTC 24 144297614 ps
T464 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.2372702696 Sep 24 02:38:12 PM UTC 24 Sep 24 02:38:24 PM UTC 24 16825524585 ps
T375 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode.1001661709 Sep 24 02:38:20 PM UTC 24 Sep 24 02:38:25 PM UTC 24 110253496 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.4140288550 Sep 24 02:38:14 PM UTC 24 Sep 24 02:38:26 PM UTC 24 3007081816 ps
T465 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_all.2284140946 Sep 24 02:38:24 PM UTC 24 Sep 24 02:38:26 PM UTC 24 35988095 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.3503164235 Sep 24 02:38:14 PM UTC 24 Sep 24 02:38:28 PM UTC 24 6886354388 ps
T466 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_csb_read.662119057 Sep 24 02:38:27 PM UTC 24 Sep 24 02:38:30 PM UTC 24 15226022 ps
T467 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_alert_test.353126718 Sep 24 02:38:27 PM UTC 24 Sep 24 02:38:30 PM UTC 24 99808802 ps
T244 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_intercept.3786693971 Sep 24 02:38:15 PM UTC 24 Sep 24 02:38:30 PM UTC 24 3492627991 ps
T468 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.1237366221 Sep 24 02:38:24 PM UTC 24 Sep 24 02:38:32 PM UTC 24 316094565 ps
T263 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_cfg_cmd.1000192062 Sep 24 02:38:20 PM UTC 24 Sep 24 02:38:32 PM UTC 24 7894637053 ps
T469 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.2740907654 Sep 24 02:38:31 PM UTC 24 Sep 24 02:38:33 PM UTC 24 12516684 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_stress_all.3424810396 Sep 24 02:38:25 PM UTC 24 Sep 24 02:38:33 PM UTC 24 2456345204 ps
T470 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_rw.1029736090 Sep 24 02:38:32 PM UTC 24 Sep 24 02:38:35 PM UTC 24 170122256 ps
T471 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.1867453915 Sep 24 02:38:33 PM UTC 24 Sep 24 02:38:37 PM UTC 24 283838394 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_all.1736137550 Sep 24 02:37:12 PM UTC 24 Sep 24 02:38:37 PM UTC 24 4949992014 ps
T232 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_intercept.3641715760 Sep 24 02:38:34 PM UTC 24 Sep 24 02:38:40 PM UTC 24 66440616 ps
T472 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.1199251537 Sep 24 02:38:30 PM UTC 24 Sep 24 02:38:43 PM UTC 24 1708407307 ps
T473 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_rw.9457651 Sep 24 02:43:13 PM UTC 24 Sep 24 02:43:17 PM UTC 24 715162297 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.2459807674 Sep 24 02:38:33 PM UTC 24 Sep 24 02:38:46 PM UTC 24 6015234106 ps
T416 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode.1549098601 Sep 24 02:38:38 PM UTC 24 Sep 24 02:38:47 PM UTC 24 91820187 ps
T203 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_stress_all.3722639828 Sep 24 02:38:47 PM UTC 24 Sep 24 02:38:50 PM UTC 24 208933392 ps
T474 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_alert_test.3321761975 Sep 24 02:38:48 PM UTC 24 Sep 24 02:38:50 PM UTC 24 22535977 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_all.1405946881 Sep 24 02:36:58 PM UTC 24 Sep 24 02:38:51 PM UTC 24 18095268075 ps
T254 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_mailbox.10396916 Sep 24 02:38:34 PM UTC 24 Sep 24 02:38:52 PM UTC 24 668378088 ps
T475 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_csb_read.2965747932 Sep 24 02:38:50 PM UTC 24 Sep 24 02:38:52 PM UTC 24 17854076 ps
T476 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.1071775032 Sep 24 02:38:53 PM UTC 24 Sep 24 02:38:55 PM UTC 24 32683713 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_all.3009876028 Sep 24 02:37:40 PM UTC 24 Sep 24 02:38:55 PM UTC 24 11217852796 ps
T248 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_upload.210189919 Sep 24 02:38:36 PM UTC 24 Sep 24 02:38:57 PM UTC 24 7491024385 ps
T223 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.3717103832 Sep 24 02:37:12 PM UTC 24 Sep 24 02:38:57 PM UTC 24 17294336419 ps
T477 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_rw.2212362414 Sep 24 02:38:54 PM UTC 24 Sep 24 02:38:57 PM UTC 24 140853843 ps
T98 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.3898619360 Sep 24 02:38:08 PM UTC 24 Sep 24 02:38:58 PM UTC 24 5750608194 ps
T398 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_mailbox.445942384 Sep 24 02:37:22 PM UTC 24 Sep 24 02:38:59 PM UTC 24 10220650777 ps
T138 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.51121206 Sep 24 02:38:06 PM UTC 24 Sep 24 02:38:59 PM UTC 24 3828427866 ps
T478 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.2527167998 Sep 24 02:38:43 PM UTC 24 Sep 24 02:39:01 PM UTC 24 3669750270 ps
T479 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.3886991123 Sep 24 02:38:59 PM UTC 24 Sep 24 02:39:01 PM UTC 24 37918967 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_cfg_cmd.1380645823 Sep 24 02:38:58 PM UTC 24 Sep 24 02:39:02 PM UTC 24 35285089 ps
T480 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_alert_test.3128387308 Sep 24 02:39:04 PM UTC 24 Sep 24 02:39:07 PM UTC 24 45164056 ps
T481 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_csb_read.1576896105 Sep 24 02:39:05 PM UTC 24 Sep 24 02:39:07 PM UTC 24 53007268 ps
T482 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.1538919610 Sep 24 02:39:00 PM UTC 24 Sep 24 02:39:08 PM UTC 24 875664072 ps
T483 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.3690804515 Sep 24 02:38:53 PM UTC 24 Sep 24 02:39:08 PM UTC 24 5903990329 ps
T124 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_all.3078729348 Sep 24 02:38:30 PM UTC 24 Sep 24 02:39:10 PM UTC 24 5056522272 ps
T220 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.3673249250 Sep 24 02:38:54 PM UTC 24 Sep 24 02:39:10 PM UTC 24 9930718339 ps
T484 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.553189715 Sep 24 02:39:09 PM UTC 24 Sep 24 02:39:12 PM UTC 24 76826807 ps
T100 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.3411370573 Sep 24 02:36:57 PM UTC 24 Sep 24 02:39:12 PM UTC 24 196646731199 ps
T444 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_rw.4042194114 Sep 24 02:39:09 PM UTC 24 Sep 24 02:39:14 PM UTC 24 1077182345 ps
T130 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_intercept.3904364921 Sep 24 02:39:12 PM UTC 24 Sep 24 02:39:16 PM UTC 24 109859023 ps
T227 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.2367379102 Sep 24 02:38:25 PM UTC 24 Sep 24 02:39:17 PM UTC 24 3074572990 ps
T485 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.2243415646 Sep 24 02:39:08 PM UTC 24 Sep 24 02:39:18 PM UTC 24 10323561518 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_intercept.4172089211 Sep 24 02:38:56 PM UTC 24 Sep 24 02:39:19 PM UTC 24 1831192660 ps
T434 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_all.3625511129 Sep 24 02:38:53 PM UTC 24 Sep 24 02:39:20 PM UTC 24 14916678774 ps
T68 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_all.1742354326 Sep 24 02:37:27 PM UTC 24 Sep 24 02:39:22 PM UTC 24 16469322462 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.3136919570 Sep 24 02:39:12 PM UTC 24 Sep 24 02:39:23 PM UTC 24 1561162570 ps
T225 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.2623811217 Sep 24 02:36:58 PM UTC 24 Sep 24 02:39:23 PM UTC 24 17487419247 ps
T486 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode.117646380 Sep 24 02:39:17 PM UTC 24 Sep 24 02:39:23 PM UTC 24 62389626 ps
T234 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_upload.2230691533 Sep 24 02:39:13 PM UTC 24 Sep 24 02:39:24 PM UTC 24 4799711239 ps
T218 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.3332348242 Sep 24 02:38:56 PM UTC 24 Sep 24 02:39:26 PM UTC 24 24679971647 ps
T487 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_alert_test.508093798 Sep 24 02:39:24 PM UTC 24 Sep 24 02:39:26 PM UTC 24 38257625 ps
T488 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_csb_read.1174281873 Sep 24 02:39:24 PM UTC 24 Sep 24 02:39:26 PM UTC 24 35199984 ps
T204 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_stress_all.738479317 Sep 24 02:39:23 PM UTC 24 Sep 24 02:39:26 PM UTC 24 206133235 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.2230687562 Sep 24 02:39:10 PM UTC 24 Sep 24 02:39:29 PM UTC 24 4618011701 ps
T131 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.2111562734 Sep 24 02:38:41 PM UTC 24 Sep 24 02:39:29 PM UTC 24 1116944193 ps
T489 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.3739926972 Sep 24 02:39:27 PM UTC 24 Sep 24 02:39:29 PM UTC 24 16218116 ps
T437 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_rw.3551792847 Sep 24 02:39:27 PM UTC 24 Sep 24 02:39:30 PM UTC 24 50626123 ps
T219 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.2514936309 Sep 24 02:37:40 PM UTC 24 Sep 24 02:39:30 PM UTC 24 20620395357 ps
T490 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_intercept.2341038569 Sep 24 02:39:30 PM UTC 24 Sep 24 02:39:35 PM UTC 24 105020617 ps
T432 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_all.1450924425 Sep 24 02:39:27 PM UTC 24 Sep 24 02:39:35 PM UTC 24 525149966 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.3680195687 Sep 24 02:39:29 PM UTC 24 Sep 24 02:39:36 PM UTC 24 302791545 ps
T224 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.306772871 Sep 24 02:36:43 PM UTC 24 Sep 24 02:39:37 PM UTC 24 55879157624 ps
T491 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.2518833559 Sep 24 02:39:27 PM UTC 24 Sep 24 02:39:37 PM UTC 24 818976492 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_cfg_cmd.2733376625 Sep 24 02:39:15 PM UTC 24 Sep 24 02:39:37 PM UTC 24 5314612827 ps
T261 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.3199877788 Sep 24 02:39:28 PM UTC 24 Sep 24 02:39:40 PM UTC 24 335988458 ps
T222 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_upload.1293556104 Sep 24 02:39:30 PM UTC 24 Sep 24 02:39:41 PM UTC 24 1089298635 ps
T492 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_alert_test.221075955 Sep 24 02:39:39 PM UTC 24 Sep 24 02:39:41 PM UTC 24 42594256 ps
T493 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_stress_all.1950225218 Sep 24 02:39:39 PM UTC 24 Sep 24 02:39:42 PM UTC 24 203592657 ps
T389 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode.4040095264 Sep 24 02:39:34 PM UTC 24 Sep 24 02:39:42 PM UTC 24 167208785 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_upload.3159399878 Sep 24 02:38:58 PM UTC 24 Sep 24 02:39:42 PM UTC 24 30658769775 ps
T221 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.1630760399 Sep 24 02:38:46 PM UTC 24 Sep 24 02:39:43 PM UTC 24 10749823708 ps
T494 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_csb_read.3654940525 Sep 24 02:39:41 PM UTC 24 Sep 24 02:39:43 PM UTC 24 226980389 ps
T495 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_cfg_cmd.2643744459 Sep 24 02:39:32 PM UTC 24 Sep 24 02:39:43 PM UTC 24 905019254 ps
T496 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.591917196 Sep 24 02:39:42 PM UTC 24 Sep 24 02:39:44 PM UTC 24 27051819 ps
T497 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.2097399873 Sep 24 02:39:42 PM UTC 24 Sep 24 02:39:45 PM UTC 24 151845930 ps
T498 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.565800929 Sep 24 02:39:19 PM UTC 24 Sep 24 02:39:46 PM UTC 24 2157276117 ps
T499 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_csb_read.1450289593 Sep 24 02:39:53 PM UTC 24 Sep 24 02:39:56 PM UTC 24 20871701 ps
T368 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.2963745457 Sep 24 02:38:21 PM UTC 24 Sep 24 02:39:46 PM UTC 24 17517707183 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_cfg_cmd.2912352654 Sep 24 02:39:45 PM UTC 24 Sep 24 02:39:49 PM UTC 24 130662297 ps
T243 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.2019934028 Sep 24 02:37:57 PM UTC 24 Sep 24 02:39:50 PM UTC 24 93516574198 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.2909474427 Sep 24 02:39:44 PM UTC 24 Sep 24 02:39:52 PM UTC 24 1268398523 ps
T237 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.2059375951 Sep 24 02:36:49 PM UTC 24 Sep 24 02:39:52 PM UTC 24 13666734385 ps
T361 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_intercept.258160664 Sep 24 02:39:44 PM UTC 24 Sep 24 02:39:52 PM UTC 24 683851446 ps
T247 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_mailbox.2215156473 Sep 24 02:39:13 PM UTC 24 Sep 24 02:39:55 PM UTC 24 4322494470 ps
T500 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_rw.566529211 Sep 24 02:39:44 PM UTC 24 Sep 24 02:39:55 PM UTC 24 198437969 ps
T501 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.176661353 Sep 24 02:39:36 PM UTC 24 Sep 24 02:39:56 PM UTC 24 2015976784 ps
T502 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_alert_test.3647392087 Sep 24 02:39:53 PM UTC 24 Sep 24 02:39:56 PM UTC 24 15803939 ps
T503 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_sts_read.3110290520 Sep 24 02:39:57 PM UTC 24 Sep 24 02:39:59 PM UTC 24 20647184 ps
T440 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_rw.1500662474 Sep 24 02:39:57 PM UTC 24 Sep 24 02:40:01 PM UTC 24 87941377 ps
T427 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_all.2557920820 Sep 24 02:39:08 PM UTC 24 Sep 24 02:40:02 PM UTC 24 7058365215 ps
T504 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode.2245110380 Sep 24 02:38:58 PM UTC 24 Sep 24 02:40:03 PM UTC 24 3711504068 ps
T418 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode.459130519 Sep 24 02:39:46 PM UTC 24 Sep 24 02:40:04 PM UTC 24 569354126 ps
T402 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_upload.3392470183 Sep 24 02:39:45 PM UTC 24 Sep 24 02:40:07 PM UTC 24 7152843320 ps
T505 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_mailbox.151022524 Sep 24 02:40:03 PM UTC 24 Sep 24 02:40:08 PM UTC 24 29137390 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_intercept.3414479685 Sep 24 02:40:02 PM UTC 24 Sep 24 02:40:08 PM UTC 24 809001891 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_cfg_cmd.3347292942 Sep 24 02:40:05 PM UTC 24 Sep 24 02:40:12 PM UTC 24 1267797048 ps
T367 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.2215499729 Sep 24 02:38:45 PM UTC 24 Sep 24 02:40:14 PM UTC 24 5070756700 ps
T506 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_read_buffer_direct.2908770013 Sep 24 02:39:47 PM UTC 24 Sep 24 02:40:14 PM UTC 24 1315831309 ps
T507 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_read_buffer_direct.2268553929 Sep 24 02:40:09 PM UTC 24 Sep 24 02:40:18 PM UTC 24 488605265 ps
T383 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_all.1279854745 Sep 24 02:39:51 PM UTC 24 Sep 24 02:40:20 PM UTC 24 5632530504 ps
T508 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_read_hw_reg.4008704844 Sep 24 02:39:55 PM UTC 24 Sep 24 02:40:22 PM UTC 24 7457398583 ps
T205 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_stress_all.2847795685 Sep 24 02:39:04 PM UTC 24 Sep 24 02:40:23 PM UTC 24 16213357914 ps
T509 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_alert_test.3991002109 Sep 24 02:40:21 PM UTC 24 Sep 24 02:40:23 PM UTC 24 14867229 ps
T414 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_pass_addr_payload_swap.2571940706 Sep 24 02:40:00 PM UTC 24 Sep 24 02:40:24 PM UTC 24 3495252238 ps
T510 /workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_csb_read.622583686 Sep 24 02:40:23 PM UTC 24 Sep 24 02:40:26 PM UTC 24 14743509 ps