Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	29923	1			T14	2		T54	16		T50	4
auto[SpiFlashAddrCfg]	6706	1			T18	10		T21	1		T25	8
auto[SpiFlashAddr3b]	8421	1			T11	2		T18	6		T21	6
auto[SpiFlashAddr4b]	6804	1			T18	4		T22	4		T23	1

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29257

1

T11

2

T14

2

T18

20

auto[1]

22597

1

T25

24

T59

14

T44

27

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27198

1

T11

2

T14

2

T18

6

auto[1]

24656

1

T18

14

T21

4

T23

1

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	34133	1			T14	2		T18	8		T54	16
values[1]	1005	1			T51	2		T137	2		T55	6
values[2]	1382	1			T21	2		T25	4		T45	5
values[3]	1373	1			T99	2		T101	2		T59	4
values[4]	1282	1			T22	4		T25	4		T49	2
values[5]	1294	1			T136	2		T101	2		T59	2
values[6]	1384	1			T11	2		T51	2		T101	4
values[7]	1271	1			T25	2		T136	2		T50	2
values[8]	8730	1			T18	12		T21	5		T23	1

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24983

1

T11

2

T14

2

T18

20

auto[1]

26871

1

T21

7

T23

1

T49

6

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

48929

1

T11

2

T14

2

T18

16

write

2925

1

T18

4

T44

2

T52

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

17275

1

T11

2

T14

2

T18

12

valids[0x1]

34579

1

T18

8

T21

1

T25

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1466	1			T50	2		T57	4		T44	2
internal_process_ops[0x5a]	1508	1			T25	2		T136	2		T99	2
internal_process_ops[0x05]	17216	1			T50	2		T51	2		T137	2
internal_process_ops[0x35]	1492	1			T57	4		T103	2		T44	3
internal_process_ops[0x15]	1363	1			T136	2		T103	2		T137	4
internal_process_ops[0x03]	926	1			T18	4		T21	1		T59	4
internal_process_ops[0x0b]	936	1			T51	2		T101	2		T59	4
internal_process_ops[0x3b]	906	1			T11	2		T21	2		T101	2
internal_process_ops[0x6b]	901	1			T18	4		T25	2		T119	2
internal_process_ops[0xbb]	939	1			T22	4		T23	1		T50	2
internal_process_ops[0xeb]	955	1			T21	4		T25	6		T103	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50434

1

T11

2

T14

2

T18

20

auto[1]

1420

1

T45

11

T62

2

T53

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49784

1

T11

2

T14

2

T18

20

auto[1]

2070

1

T44

2

T56

4

T45

16

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8150

1

T14

2

T54

16

T50

4

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5214

1

T62

2

T53

3

T60

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1675

1

T18

6

T136

2

T50

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1505

1

T25

8

T59

4

T53

3

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2097

1

T11

2

T18

6

T136

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1830

1

T25

10

T59

6

T62

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1622

1

T18

4

T22

4

T136

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1545

1

T25

6

T59

4

T53

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

82

1

T52

2

T61

1

T135

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

77

1

T36

1

T47

1

T67

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

80

1

T47

6

T216

1

T217

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

90

1

T47

2

T218

4

T219

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

106

1

T18

4

T53

2

T135

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

84

1

T62

2

T61

1

T47

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

91

1

T47

1

T67

1

T68

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

87

1

T61

2

T64

2

T65

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

92

1

T53

1

T47

2

T220

6

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

59

1

T53

1

T68

1

T219

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

86

1

T47

1

T131

2

T221

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

78

1

T53

1

T60

2

T47

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

108

1

T61

1

T109

2

T222

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

77

1

T47

1

T67

2

T68

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

77

1

T95

1

T68

1

T207

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

71

1

T63

2

T47

1

T67

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9499

1

T44

17

T45

252

T48

39

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6343

1

T44

8

T45

258

T48

17

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1365

1

T21

1

T44

1

T45

6

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1421

1

T44

3

T45

16

T48

12

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1901

1

T21

6

T49

2

T44

5

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1860

1

T44

10

T45

18

T48

14

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1473

1

T23

1

T49

4

T44

9

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1429

1

T44

5

T45

15

T48

10

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

99

1

T44

1

T45

1

T48

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

79

1

T46

1

T138

2

T114

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

112

1

T45

1

T223

1

T224

8

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

98

1

T45

1

T46

2

T98

5

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

104

1

T94

1

T46

1

T223

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

79

1

T45

1

T225

3

T226

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

92

1

T45

3

T94

2

T98

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

97

1

T45

3

T98

1

T138

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

131

1

T45

5

T98

2

T138

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

105

1

T46

2

T138

1

T225

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

82

1

T227

3

T225

1

T224

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

100

1

T45

3

T48

6

T138

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

64

1

T45

2

T46

1

T98

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

129

1

T45

1

T48

3

T46

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

99

1

T44

1

T45

2

T48

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

110

1

T45

2

T48

2

T46

3

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3220	1			T14	2		T54	16		T58	10
auto[0]	values[0]	valids[0x1]	12594	1			T18	8		T50	4		T51	2
auto[0]	values[1]	valids[0x1]	488	1			T51	2		T137	2		T55	6
auto[0]	values[2]	valids[0x0]	474	1			T25	2		T75	2		T228	2
auto[0]	values[2]	valids[0x1]	260	1			T25	2		T36	2		T63	2
auto[0]	values[3]	valids[0x0]	435	1			T101	2		T52	2		T229	6
auto[0]	values[3]	valids[0x1]	257	1			T99	2		T59	4		T47	5
auto[0]	values[4]	valids[0x0]	418	1			T22	4		T77	2		T53	1
auto[0]	values[4]	valids[0x1]	234	1			T25	4		T53	1		T61	1
auto[0]	values[5]	valids[0x0]	476	1			T59	2		T77	2		T62	2
auto[0]	values[5]	valids[0x1]	222	1			T136	2		T101	2		T53	1
auto[0]	values[6]	valids[0x0]	410	1			T11	2		T101	4		T77	2
auto[0]	values[6]	valids[0x1]	281	1			T51	2		T61	2		T230	2
auto[0]	values[7]	valids[0x0]	449	1			T25	2		T50	2		T51	4
auto[0]	values[7]	valids[0x1]	203	1			T136	2		T62	1		T53	1
auto[0]	values[8]	valids[0x0]	2861	1			T18	12		T25	8		T119	2
auto[0]	values[8]	valids[0x1]	1701	1			T25	6		T136	2		T51	4
auto[1]	values[0]	valids[0x0]	3805	1			T44	19		T45	34		T48	24
auto[1]	values[0]	valids[0x1]	14514	1			T49	2		T44	15		T45	508
auto[1]	values[1]	valids[0x1]	517	1			T44	3		T45	5		T48	4
auto[1]	values[2]	valids[0x0]	396	1			T21	2		T45	5		T48	2
auto[1]	values[2]	valids[0x1]	252	1			T46	5		T98	3		T138	4
auto[1]	values[3]	valids[0x0]	419	1			T44	1		T45	3		T46	7
auto[1]	values[3]	valids[0x1]	262	1			T45	1		T48	2		T46	2
auto[1]	values[4]	valids[0x0]	354	1			T49	2		T45	2		T48	2
auto[1]	values[4]	valids[0x1]	276	1			T44	1		T48	5		T46	1
auto[1]	values[5]	valids[0x0]	317	1			T44	2		T45	4		T76	1
auto[1]	values[5]	valids[0x1]	279	1			T45	1		T94	1		T46	3
auto[1]	values[6]	valids[0x0]	424	1			T45	7		T48	3		T46	4
auto[1]	values[6]	valids[0x1]	269	1			T44	1		T45	1		T48	2
auto[1]	values[7]	valids[0x0]	367	1			T44	3		T45	3		T48	4
auto[1]	values[7]	valids[0x1]	252	1			T44	1		T45	3		T48	2
auto[1]	values[8]	valids[0x0]	2450	1			T21	4		T23	1		T44	7
auto[1]	values[8]	valids[0x1]	1718	1			T21	1		T49	2		T44	7