Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3064454

1

T6

1

T10

1

T11

9858

auto[1]

28192

1

T44

19

T56

35

T45

445

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

940012

1

T6

1

T10

1

T11

9858

auto[1]

2152634

1

T50

1024

T51

512

T103

768

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	552624	1			T6	1		T10	1		T11	3449
auto[524288:1048575]	338536	1			T21	2		T22	534		T54	1
auto[1048576:1572863]	361050	1			T11	917		T15	1		T23	5
auto[1572864:2097151]	365366	1			T22	468		T50	195		T120	867
auto[2097152:2621439]	350533	1			T21	56		T57	782		T99	46
auto[2621440:3145727]	353231	1			T11	1435		T15	1		T22	2
auto[3145728:3670015]	424620	1			T11	4057		T54	447		T50	193
auto[3670016:4194303]	346686	1			T21	2		T54	3		T50	1095

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2184409

1

T6

1

T10

1

T11

13

auto[1]

908237

1

T11

9845

T15

301

T21

204

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2637307

1

T6

1

T10

1

T11

9858

auto[1]

455339

1

T14

2

T54

1842

T44

276

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	185105	1			T6	1		T10	1		T11	3449
auto[0]	auto[0]	auto[0:524287]	auto[1]	308132	1			T50	505		T51	512		T137	8128
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	106746	1			T21	2		T22	534		T54	1
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	177387	1			T103	128		T44	904		T45	2164
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	104807	1			T11	917		T15	1		T23	5
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	175830	1			T103	1		T44	256		T45	4819
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	85427	1			T22	468		T50	195		T120	867
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	199218	1			T44	5		T74	2		T147	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	75976	1			T21	56		T57	782		T99	46
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	219758	1			T103	512		T44	1		T45	1290
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	101797	1			T11	1435		T15	1		T22	2
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	198846	1			T45	1271		T61	512		T147	502
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	167017	1			T11	4057		T54	447		T50	193
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	212954	1			T45	390		T48	4		T147	230
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	96074	1			T21	2		T50	576		T99	795
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	200789	1			T50	519		T103	127		T45	519
auto[0]	auto[1]	auto[0:524287]	auto[0]	3976	1			T14	2		T54	4		T45	4
auto[0]	auto[1]	auto[0:524287]	auto[1]	51480	1			T45	257		T62	256		T53	1
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	683	1			T45	1		T97	51		T48	26
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	50553	1			T45	1		T48	1537		T46	2514
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	2363	1			T54	885		T44	2		T61	11
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	73735	1			T61	512		T46	5		T47	259
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	992	1			T44	18		T45	1		T97	37
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	77251	1			T44	256		T45	715		T46	1202
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	684	1			T45	5		T97	1		T61	7
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	49927	1			T45	2164		T61	4		T46	514
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1721	1			T54	950		T97	74		T36	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	47449	1			T45	512		T36	512		T68	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	811	1			T45	3		T97	2		T61	22
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	39959	1			T45	2		T61	256		T63	2150
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	2234	1			T54	3		T45	2		T61	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	44773	1			T45	1		T227	1		T224	133
auto[1]	auto[0]	auto[0:524287]	auto[0]	516	1			T44	13		T56	4		T45	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	2652	1			T56	31		T45	26		T63	25
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	353	1			T44	4		T45	5		T48	3
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2152	1			T45	83		T94	1		T46	42
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	322	1			T36	1		T47	1		T67	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	3453	1			T48	482		T47	3		T67	23
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	334	1			T47	1		T223	1		T100	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1484	1			T47	14		T223	1		T68	29
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	416	1			T45	1		T53	2		T47	4
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	3142	1			T45	32		T53	6		T47	183
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	297	1			T45	1		T36	2		T46	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2627	1			T45	2		T36	81		T46	36
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	319	1			T45	1		T48	14		T36	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1578	1			T45	14		T36	11		T46	71
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	370	1			T44	2		T45	1		T61	5
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1429	1			T45	33		T46	1		T67	41
auto[1]	auto[1]	auto[0:524287]	auto[0]	109	1			T45	1		T53	1		T46	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	654	1			T45	42		T46	30		T243	40
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	92	1			T45	1		T138	2		T390	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	570	1			T45	26		T390	6		T391	52
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	70	1			T47	3		T114	1		T217	4
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	470	1			T47	70		T114	38		T217	22
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	49	1			T48	6		T237	2		T226	4
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	611	1			T48	399		T237	3		T359	12
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	71	1			T45	1		T46	2		T114	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	559	1			T45	54		T46	15		T114	60
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	63	1			T68	1		T207	1		T226	4
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	431	1			T68	25		T207	13		T392	30
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	124	1			T45	2		T63	1		T138	8
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	1858	1			T45	68		T63	32		T138	256
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	94	1			T45	1		T227	1		T224	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	923	1			T45	48		T224	2		T393	3

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1716892	1			T6	1		T10	1		T11	13
auto[0]	auto[0]	auto[1]	898971	1			T11	9845		T15	301		T21	204
auto[0]	auto[1]	auto[0]	439923	1			T14	2		T54	9		T44	276
auto[0]	auto[1]	auto[1]	8668	1			T54	1833		T45	2		T97	204
auto[1]	auto[0]	auto[0]	20969	1			T44	17		T56	33		T45	201
auto[1]	auto[0]	auto[1]	475	1			T44	2		T56	2		T61	1
auto[1]	auto[1]	auto[0]	6625	1			T45	244		T53	1		T48	404
auto[1]	auto[1]	auto[1]	123	1			T48	1		T46	2		T47	1