Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2455223	1			T1	1		T2	1		T3	1
all_pins[1]	2455223	1			T1	1		T2	1		T3	1
all_pins[2]	2455223	1			T1	1		T2	1		T3	1
all_pins[3]	2455223	1			T1	1		T2	1		T3	1
all_pins[4]	2455223	1			T1	1		T2	1		T3	1
all_pins[5]	2455223	1			T1	1		T2	1		T3	1
all_pins[6]	2455223	1			T1	1		T2	1		T3	1
all_pins[7]	2455223	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	19548571	1			T1	8		T2	8		T3	8
values[0x1]	93213	1			T8	16		T26	12		T35	25
transitions[0x0=>0x1]	92655	1			T8	10		T26	9		T35	21
transitions[0x1=>0x0]	92669	1			T8	10		T26	9		T35	21

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2454690	1			T1	1		T2	1		T3	1
all_pins[0]	values[0x1]	533	1			T8	2		T26	1		T35	3
all_pins[0]	transitions[0x0=>0x1]	379	1			T26	1		T35	3		T36	2
all_pins[0]	transitions[0x1=>0x0]	236	1			T8	1		T26	1		T35	6
all_pins[1]	values[0x0]	2454833	1			T1	1		T2	1		T3	1
all_pins[1]	values[0x1]	390	1			T8	3		T26	1		T35	6
all_pins[1]	transitions[0x0=>0x1]	340	1			T8	2		T35	5		T36	1
all_pins[1]	transitions[0x1=>0x0]	214	1			T8	1		T26	2		T35	2
all_pins[2]	values[0x0]	2454959	1			T1	1		T2	1		T3	1
all_pins[2]	values[0x1]	264	1			T8	2		T26	3		T35	3
all_pins[2]	transitions[0x0=>0x1]	220	1			T26	2		T35	2		T36	3
all_pins[2]	transitions[0x1=>0x0]	155	1			T26	2		T35	1		T36	2
all_pins[3]	values[0x0]	2455024	1			T1	1		T2	1		T3	1
all_pins[3]	values[0x1]	199	1			T8	2		T26	3		T35	2
all_pins[3]	transitions[0x0=>0x1]	151	1			T8	2		T26	3		T35	2
all_pins[3]	transitions[0x1=>0x0]	178	1			T8	3		T35	3		T36	4
all_pins[4]	values[0x0]	2454997	1			T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	226	1			T8	3		T35	3		T36	4
all_pins[4]	transitions[0x0=>0x1]	175	1			T8	3		T35	2		T36	2
all_pins[4]	transitions[0x1=>0x0]	1378	1			T8	2		T26	2		T35	2
all_pins[5]	values[0x0]	2453794	1			T1	1		T2	1		T3	1
all_pins[5]	values[0x1]	1429	1			T8	2		T26	2		T35	3
all_pins[5]	transitions[0x0=>0x1]	1323	1			T8	1		T26	1		T35	2
all_pins[5]	transitions[0x1=>0x0]	89876	1			T8	1		T26	1		T35	4
all_pins[6]	values[0x0]	2365241	1			T1	1		T2	1		T3	1
all_pins[6]	values[0x1]	89982	1			T8	2		T26	2		T35	5
all_pins[6]	transitions[0x0=>0x1]	89930	1			T8	2		T26	2		T35	5
all_pins[6]	transitions[0x1=>0x0]	138	1			T36	3		T37	2		T203	3
all_pins[7]	values[0x0]	2455033	1			T1	1		T2	1		T3	1
all_pins[7]	values[0x1]	190	1			T36	3		T37	4		T203	5
all_pins[7]	transitions[0x0=>0x1]	137	1			T36	1		T37	4		T203	4
all_pins[7]	transitions[0x1=>0x0]	494	1			T8	2		T26	1		T35	3