Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14229

1

T11

2

T14

2

T18

20

auto[1]

10754

1

T25

24

T59

14

T62

4

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2700	1			T18	20		T50	6		T58	10
values[1]	3517	1			T11	2		T137	22		T52	14
values[2]	3169	1			T14	2		T22	4		T25	24
values[3]	3712	1			T103	6		T70	4		T228	8
values[4]	2608	1			T54	16		T56	49		T239	4
values[5]	3202	1			T62	20		T36	21		T229	8
values[6]	3035	1			T119	2		T51	16		T57	10
values[7]	3040	1			T101	14		T97	14		T61	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2889	1			T25	24		T56	49		T259	4
values[1]	3352	1			T57	10		T99	2		T97	14
values[2]	3191	1			T14	2		T22	4		T55	24
values[3]	2823	1			T54	16		T50	6		T103	6
values[4]	2829	1			T11	2		T53	28		T70	4
values[5]	2625	1			T119	2		T137	22		T60	12
values[6]	4413	1			T18	20		T136	6		T51	16
values[7]	2861	1			T101	14		T59	14		T62	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	298	1			T47	11		T68	14		T243	8
auto[0]	values[0]	values[1]	178	1			T395	4		T237	23		T245	4
auto[0]	values[0]	values[2]	142	1			T55	24		T61	17		T275	9
auto[0]	values[0]	values[3]	201	1			T50	6		T147	12		T100	16
auto[0]	values[0]	values[4]	123	1			T142	10		T236	6		T88	8
auto[0]	values[0]	values[5]	222	1			T296	94		T320	15		T316	17
auto[0]	values[0]	values[6]	298	1			T18	20		T58	10		T78	2
auto[0]	values[0]	values[7]	205	1			T314	6		T296	12		T308	62
auto[0]	values[1]	values[0]	283	1			T36	11		T148	4		T109	49
auto[0]	values[1]	values[1]	374	1			T68	15		T268	87		T217	16
auto[0]	values[1]	values[2]	361	1			T74	2		T47	17		T100	15
auto[0]	values[1]	values[3]	303	1			T52	14		T61	14		T396	50
auto[0]	values[1]	values[4]	175	1			T11	2		T222	4		T397	22
auto[0]	values[1]	values[5]	242	1			T137	22		T36	102		T47	15
auto[0]	values[1]	values[6]	168	1			T129	4		T243	11		T237	11
auto[0]	values[1]	values[7]	169	1			T237	10		T280	13		T314	15
auto[0]	values[2]	values[0]	227	1			T259	4		T254	10		T237	23
auto[0]	values[2]	values[1]	264	1			T110	20		T369	8		T217	13
auto[0]	values[2]	values[2]	338	1			T14	2		T22	4		T77	12
auto[0]	values[2]	values[3]	124	1			T68	11		T131	15		T303	16
auto[0]	values[2]	values[4]	187	1			T53	22		T63	37		T232	4
auto[0]	values[2]	values[5]	233	1			T63	10		T68	72		T237	27
auto[0]	values[2]	values[6]	392	1			T136	6		T216	45		T246	12
auto[0]	values[2]	values[7]	187	1			T271	4		T267	7		T337	8
auto[0]	values[3]	values[0]	93	1			T131	9		T279	18		T269	20
auto[0]	values[3]	values[1]	337	1			T47	10		T398	16		T243	10
auto[0]	values[3]	values[2]	300	1			T228	8		T47	50		T219	11
auto[0]	values[3]	values[3]	188	1			T103	6		T283	8		T323	13
auto[0]	values[3]	values[4]	92	1			T217	17		T233	20		T277	12
auto[0]	values[3]	values[5]	165	1			T67	11		T237	9		T320	9
auto[0]	values[3]	values[6]	435	1			T293	10		T205	16		T262	14
auto[0]	values[3]	values[7]	267	1			T68	44		T267	8		T276	8
auto[0]	values[4]	values[0]	222	1			T56	49		T67	10		T258	20
auto[0]	values[4]	values[1]	297	1			T100	12		T373	16		T280	13
auto[0]	values[4]	values[2]	86	1			T272	12		T275	9		T399	14
auto[0]	values[4]	values[3]	112	1			T54	16		T239	4		T47	15
auto[0]	values[4]	values[4]	183	1			T400	10		T233	17		T321	9
auto[0]	values[4]	values[5]	162	1			T220	20		T366	10		T401	20
auto[0]	values[4]	values[6]	185	1			T131	12		T237	25		T270	14
auto[0]	values[4]	values[7]	171	1			T288	18		T243	54		T252	13
auto[0]	values[5]	values[0]	141	1			T100	9		T132	11		T269	9
auto[0]	values[5]	values[1]	205	1			T219	43		T402	12		T323	11
auto[0]	values[5]	values[2]	236	1			T219	10		T240	14		T246	14
auto[0]	values[5]	values[3]	167	1			T244	2		T248	10		T267	9
auto[0]	values[5]	values[4]	255	1			T290	4		T403	2		T241	6
auto[0]	values[5]	values[5]	121	1			T229	8		T404	6		T270	12
auto[0]	values[5]	values[6]	318	1			T36	11		T47	10		T100	15
auto[0]	values[5]	values[7]	218	1			T62	16		T217	36		T405	16
auto[0]	values[6]	values[0]	179	1			T68	10		T221	12		T269	17
auto[0]	values[6]	values[1]	170	1			T57	10		T99	2		T255	2
auto[0]	values[6]	values[2]	276	1			T130	2		T237	17		T247	2
auto[0]	values[6]	values[3]	229	1			T95	14		T252	11		T313	11
auto[0]	values[6]	values[4]	341	1			T263	16		T47	116		T274	22
auto[0]	values[6]	values[5]	227	1			T119	2		T243	46		T357	18
auto[0]	values[6]	values[6]	426	1			T51	16		T285	6		T237	16
auto[0]	values[6]	values[7]	149	1			T252	9		T321	10		T325	18
auto[0]	values[7]	values[0]	108	1			T286	4		T277	10		T406	15
auto[0]	values[7]	values[1]	207	1			T97	14		T75	2		T135	20
auto[0]	values[7]	values[2]	104	1			T256	10		T67	12		T131	8
auto[0]	values[7]	values[3]	233	1			T221	10		T243	50		T246	7
auto[0]	values[7]	values[4]	231	1			T67	12		T132	12		T314	18
auto[0]	values[7]	values[5]	182	1			T237	13		T249	10		T323	7
auto[0]	values[7]	values[6]	268	1			T61	10		T219	12		T237	11
auto[0]	values[7]	values[7]	249	1			T101	14		T219	10		T261	18
auto[1]	values[0]	values[0]	262	1			T47	68		T68	6		T243	53
auto[1]	values[0]	values[1]	104	1			T237	8		T235	4		T339	5
auto[1]	values[0]	values[2]	67	1			T61	3		T275	11		T313	7
auto[1]	values[0]	values[3]	106	1			T100	4		T131	10		T205	12
auto[1]	values[0]	values[4]	63	1			T407	16		T82	4		T306	10
auto[1]	values[0]	values[5]	130	1			T296	16		T320	5		T316	6
auto[1]	values[0]	values[6]	175	1			T47	76		T68	13		T314	9
auto[1]	values[0]	values[7]	126	1			T314	14		T296	12		T308	11
auto[1]	values[1]	values[0]	274	1			T36	9		T47	9		T270	36
auto[1]	values[1]	values[1]	129	1			T68	5		T217	8		T327	11
auto[1]	values[1]	values[2]	168	1			T230	8		T47	3		T100	5
auto[1]	values[1]	values[3]	252	1			T61	6		T250	12		T296	58
auto[1]	values[1]	values[4]	298	1			T408	12		T321	29		T311	26
auto[1]	values[1]	values[5]	108	1			T60	12		T36	13		T47	5
auto[1]	values[1]	values[6]	100	1			T243	9		T237	9		T233	7
auto[1]	values[1]	values[7]	113	1			T237	10		T280	10		T314	5
auto[1]	values[2]	values[0]	190	1			T25	24		T242	6		T237	9
auto[1]	values[2]	values[1]	137	1			T217	8		T265	13		T308	19
auto[1]	values[2]	values[2]	242	1			T53	9		T67	10		T243	10
auto[1]	values[2]	values[3]	92	1			T68	13		T131	5		T303	28
auto[1]	values[2]	values[4]	128	1			T53	6		T63	11		T68	7
auto[1]	values[2]	values[5]	153	1			T63	43		T68	7		T237	14
auto[1]	values[2]	values[6]	139	1			T216	10		T246	8		T323	8
auto[1]	values[2]	values[7]	136	1			T267	13		T337	12		T305	2
auto[1]	values[3]	values[0]	136	1			T131	11		T269	8		T409	10
auto[1]	values[3]	values[1]	356	1			T47	79		T243	24		T296	107
auto[1]	values[3]	values[2]	254	1			T47	10		T219	9		T246	8
auto[1]	values[3]	values[3]	135	1			T323	7		T269	15		T410	18
auto[1]	values[3]	values[4]	88	1			T70	4		T217	53		T233	20
auto[1]	values[3]	values[5]	154	1			T67	33		T284	2		T237	12
auto[1]	values[3]	values[6]	496	1			T218	18		T205	4		T309	16
auto[1]	values[3]	values[7]	216	1			T68	54		T267	12		T270	9
auto[1]	values[4]	values[0]	129	1			T67	10		T217	34		T132	8
auto[1]	values[4]	values[1]	215	1			T100	8		T280	13		T275	11
auto[1]	values[4]	values[2]	108	1			T275	11		T411	18		T412	18
auto[1]	values[4]	values[3]	80	1			T47	48		T266	6		T339	8
auto[1]	values[4]	values[4]	139	1			T233	3		T321	11		T82	15
auto[1]	values[4]	values[5]	108	1			T253	11		T82	51		T413	18
auto[1]	values[4]	values[6]	286	1			T131	8		T237	37		T270	6
auto[1]	values[4]	values[7]	125	1			T66	4		T243	8		T252	15
auto[1]	values[5]	values[0]	134	1			T100	11		T132	9		T269	11
auto[1]	values[5]	values[1]	141	1			T219	8		T323	9		T270	7
auto[1]	values[5]	values[2]	220	1			T219	13		T246	6		T233	10
auto[1]	values[5]	values[3]	219	1			T267	11		T266	62		T253	9
auto[1]	values[5]	values[4]	225	1			T69	16		T267	9		T233	7
auto[1]	values[5]	values[5]	100	1			T270	8		T320	13		T316	10
auto[1]	values[5]	values[6]	315	1			T36	10		T47	186		T100	5
auto[1]	values[5]	values[7]	187	1			T62	4		T217	10		T321	11
auto[1]	values[6]	values[0]	125	1			T68	36		T221	29		T269	6
auto[1]	values[6]	values[1]	121	1			T68	10		T294	8		T296	5
auto[1]	values[6]	values[2]	132	1			T237	9		T269	5		T270	5
auto[1]	values[6]	values[3]	135	1			T95	6		T370	22		T252	9
auto[1]	values[6]	values[4]	166	1			T47	10		T221	7		T414	6
auto[1]	values[6]	values[5]	86	1			T243	11		T269	9		T81	11
auto[1]	values[6]	values[6]	139	1			T237	4		T323	12		T253	4
auto[1]	values[6]	values[7]	134	1			T59	14		T252	11		T321	10
auto[1]	values[7]	values[0]	88	1			T65	6		T277	10		T386	20
auto[1]	values[7]	values[1]	117	1			T310	4		T292	17		T233	8
auto[1]	values[7]	values[2]	157	1			T67	50		T131	12		T237	5
auto[1]	values[7]	values[3]	247	1			T221	36		T243	4		T246	28
auto[1]	values[7]	values[4]	135	1			T64	8		T67	8		T132	8
auto[1]	values[7]	values[5]	232	1			T237	11		T323	13		T270	12
auto[1]	values[7]	values[6]	273	1			T61	10		T219	8		T237	11
auto[1]	values[7]	values[7]	209	1			T219	77		T221	16		T296	5