Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	335	1			T50	2		T53	2		T61	2
auto[ReadAddrCrossIntoMailbox]	275	1			T53	2		T61	4		T63	2
auto[ReadAddrCrossOutOfMailbox]	272	1			T53	2		T61	1		T63	1
auto[ReadAddrCrossAllMailbox]	175	1			T61	3		T63	1		T95	1
auto[ReadAddrOutsideMailbox]	2965	1			T11	2		T18	8		T22	4

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1929

1

T11

1

T18

4

T22

2

auto[1]

2093

1

T11

1

T18

4

T22

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	654	1			T18	4		T59	4		T137	4
read_ops[0x0b]	691	1			T51	2		T101	2		T59	4
read_ops[0x3b]	645	1			T11	2		T101	2		T55	2
read_ops[0x6b]	646	1			T18	4		T25	2		T55	2
read_ops[0xbb]	701	1			T22	4		T50	2		T51	4
read_ops[0xeb]	685	1			T25	6		T103	2		T59	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T61	1		T47	3		T68	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	28	1			T246	2		T401	1		T266	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T229	1		T47	2		T100	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T53	1		T229	1		T100	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T53	1		T61	1		T68	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T47	1		T131	1		T237	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T95	1		T254	2		T237	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T254	2		T243	1		T207	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	232	1			T18	2		T59	2		T137	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	227	1			T18	2		T59	2		T137	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T244	1		T47	1		T68	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	24	1			T53	1		T61	1		T244	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T53	1		T47	1		T296	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T61	2		T100	1		T131	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T67	1		T219	2		T237	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T47	2		T68	2		T131	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	9	1			T68	1		T237	1		T249	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T61	1		T249	1		T314	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	236	1			T51	1		T101	1		T59	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	282	1			T51	1		T101	1		T59	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	23	1			T142	1		T221	1		T207	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	21	1			T142	1		T47	1		T237	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	15	1			T255	1		T68	1		T275	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T63	1		T255	1		T47	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	9	1			T401	1		T270	2		T415	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T63	1		T47	1		T67	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T219	1		T401	1		T253	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T63	1		T131	1		T401	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	240	1			T11	1		T101	1		T55	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	260	1			T11	1		T101	1		T55	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T53	1		T47	1		T283	3
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	26	1			T47	1		T283	3		T237	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	16	1			T401	1		T252	1		T315	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T63	1		T296	1		T401	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	16	1			T47	1		T68	1		T237	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T53	1		T47	1		T266	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T67	1		T237	1		T296	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T68	1		T401	1		T269	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	232	1			T18	2		T25	1		T55	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	249	1			T18	2		T25	1		T55	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T50	1		T142	1		T47	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T50	1		T142	1		T100	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T376	1		T401	1		T266	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	36	1			T61	1		T95	1		T100	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T68	1		T221	1		T237	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T217	1		T401	1		T233	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	9	1			T237	1		T277	1		T275	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T47	1		T68	1		T243	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	248	1			T22	2		T51	2		T101	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	259	1			T22	2		T51	2		T101	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	27	1			T221	1		T267	1		T270	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	28	1			T67	1		T243	1		T237	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T229	2		T68	1		T131	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T61	1		T229	2		T67	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T47	1		T68	1		T249	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T67	1		T100	1		T237	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T61	2		T131	1		T292	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T131	1		T376	1		T233	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	228	1			T25	3		T103	1		T59	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	272	1			T25	3		T103	1		T59	1