Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.63	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	2	126	98.44

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	2	126	98.44	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3195	1			T52	14		T53	28		T110	20
values[1]	3076	1			T101	14		T62	20		T61	20
values[2]	3106	1			T18	20		T119	2		T50	6
values[3]	2934	1			T11	2		T25	24		T99	2
values[4]	3485	1			T22	4		T136	6		T59	14
values[5]	2912	1			T58	10		T77	12		T53	22
values[6]	3141	1			T54	16		T57	10		T47	196
values[7]	3134	1			T14	2		T231	2		T36	21

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2842	1			T14	2		T101	14		T53	22
values[1]	2535	1			T22	4		T77	12		T78	2
values[2]	3350	1			T60	12		T61	20		T74	2
values[3]	3747	1			T11	2		T56	49		T135	20
values[4]	3222	1			T103	6		T137	22		T61	20
values[5]	2753	1			T18	20		T25	24		T119	2
values[6]	3242	1			T99	2		T58	10		T62	20
values[7]	3292	1			T136	6		T50	6		T57	10

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24360

1

T11

2

T14

2

T18

20

auto[1]

623

1

T62

2

T53

2

T60

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	2	126	98.44	2

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[3]]	[values[5]]	0	1	1
[auto[1]]	[values[6]]	[values[1]]	0	1	1

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	375	1			T142	10		T68	24		T219	84
auto[0]	values[0]	values[1]	357	1			T53	27		T232	4		T233	19
auto[0]	values[0]	values[2]	412	1			T234	12		T219	20		T235	4
auto[0]	values[0]	values[3]	465	1			T130	2		T68	20		T236	6
auto[0]	values[0]	values[4]	363	1			T100	20		T237	20		T238	12
auto[0]	values[0]	values[5]	230	1			T52	14		T239	4		T68	20
auto[0]	values[0]	values[6]	355	1			T110	20		T217	45		T240	14
auto[0]	values[0]	values[7]	554	1			T68	79		T217	45		T241	6
auto[0]	values[1]	values[0]	410	1			T101	14		T242	6		T243	62
auto[0]	values[1]	values[1]	253	1			T75	2		T228	8		T237	20
auto[0]	values[1]	values[2]	405	1			T244	2		T100	20		T245	4
auto[0]	values[1]	values[3]	397	1			T135	20		T47	19		T237	22
auto[0]	values[1]	values[4]	365	1			T61	20		T207	20		T246	18
auto[0]	values[1]	values[5]	293	1			T64	6		T65	2		T247	2
auto[0]	values[1]	values[6]	302	1			T62	18		T129	4		T248	10
auto[0]	values[1]	values[7]	580	1			T67	20		T100	17		T243	20
auto[0]	values[2]	values[0]	466	1			T243	60		T249	10		T250	12
auto[0]	values[2]	values[1]	195	1			T251	33		T252	20		T253	33
auto[0]	values[2]	values[2]	482	1			T61	19		T254	10		T237	21
auto[0]	values[2]	values[3]	501	1			T255	2		T256	10		T47	59
auto[0]	values[2]	values[4]	366	1			T103	6		T100	20		T257	18
auto[0]	values[2]	values[5]	331	1			T18	20		T119	2		T51	16
auto[0]	values[2]	values[6]	375	1			T229	8		T219	22		T258	20
auto[0]	values[2]	values[7]	300	1			T50	6		T259	4		T148	4
auto[0]	values[3]	values[0]	350	1			T47	20		T67	60		T131	20
auto[0]	values[3]	values[1]	325	1			T78	2		T67	18		T260	28
auto[0]	values[3]	values[2]	411	1			T74	2		T47	78		T261	18
auto[0]	values[3]	values[3]	365	1			T11	2		T56	49		T109	49
auto[0]	values[3]	values[4]	473	1			T220	20		T217	34		T262	14
auto[0]	values[3]	values[5]	240	1			T25	24		T36	20		T263	16
auto[0]	values[3]	values[6]	502	1			T99	2		T69	14		T246	33
auto[0]	values[3]	values[7]	193	1			T264	2		T265	21		T266	17
auto[0]	values[4]	values[0]	179	1			T47	20		T237	21		T267	20
auto[0]	values[4]	values[1]	450	1			T22	4		T237	25		T268	87
auto[0]	values[4]	values[2]	489	1			T60	10		T269	27		T270	43
auto[0]	values[4]	values[3]	503	1			T47	124		T68	46		T271	4
auto[0]	values[4]	values[4]	570	1			T137	22		T63	53		T237	30
auto[0]	values[4]	values[5]	503	1			T59	14		T63	46		T47	80
auto[0]	values[4]	values[6]	329	1			T237	20		T272	12		T273	12
auto[0]	values[4]	values[7]	388	1			T136	6		T55	24		T61	18
auto[0]	values[5]	values[0]	481	1			T53	21		T95	20		T205	17
auto[0]	values[5]	values[1]	274	1			T77	12		T68	19		T221	23
auto[0]	values[5]	values[2]	480	1			T274	22		T233	19		T275	18
auto[0]	values[5]	values[3]	298	1			T68	20		T243	33		T207	24
auto[0]	values[5]	values[4]	162	1			T243	20		T267	20		T233	18
auto[0]	values[5]	values[5]	387	1			T147	12		T67	20		T276	8
auto[0]	values[5]	values[6]	313	1			T58	10		T70	4		T66	2
auto[0]	values[5]	values[7]	435	1			T67	43		T68	30		T221	66
auto[0]	values[6]	values[0]	272	1			T216	48		T132	19		T277	20
auto[0]	values[6]	values[1]	375	1			T47	196		T278	22		T279	18
auto[0]	values[6]	values[2]	403	1			T219	20		T280	26		T266	57
auto[0]	values[6]	values[3]	642	1			T237	20		T281	6		T282	22
auto[0]	values[6]	values[4]	598	1			T283	8		T219	49		T284	2
auto[0]	values[6]	values[5]	207	1			T54	16		T285	6		T269	20
auto[0]	values[6]	values[6]	270	1			T131	18		T286	4		T287	18
auto[0]	values[6]	values[7]	307	1			T57	10		T288	18		T243	33
auto[0]	values[7]	values[0]	222	1			T14	2		T269	20		T289	12
auto[0]	values[7]	values[1]	260	1			T47	63		T68	44		T290	4
auto[0]	values[7]	values[2]	184	1			T131	20		T267	17		T291	20
auto[0]	values[7]	values[3]	471	1			T36	21		T47	128		T292	18
auto[0]	values[7]	values[4]	250	1			T293	10		T243	20		T294	4
auto[0]	values[7]	values[5]	500	1			T231	2		T243	57		T237	23
auto[0]	values[7]	values[6]	709	1			T246	80		T295	8		T296	44
auto[0]	values[7]	values[7]	458	1			T297	14		T298	2		T299	22
auto[1]	values[0]	values[0]	15	1			T219	3		T300	6		T301	3
auto[1]	values[0]	values[1]	12	1			T53	1		T233	1		T302	1
auto[1]	values[0]	values[2]	6	1			T269	1		T303	1		T304	1
auto[1]	values[0]	values[3]	9	1			T267	3		T305	1		T82	1
auto[1]	values[0]	values[4]	8	1			T306	2		T307	6		-	-
auto[1]	values[0]	values[5]	11	1			T218	4		T246	2		T252	3
auto[1]	values[0]	values[6]	8	1			T217	1		T296	1		T308	1
auto[1]	values[0]	values[7]	15	1			T217	1		T309	4		T252	2
auto[1]	values[1]	values[0]	5	1			T310	2		T311	1		T312	2
auto[1]	values[1]	values[1]	3	1			T313	2		T84	1		-	-
auto[1]	values[1]	values[2]	6	1			T314	2		T315	1		T302	2
auto[1]	values[1]	values[3]	15	1			T47	1		T237	4		T308	1
auto[1]	values[1]	values[4]	15	1			T246	2		T269	3		T308	3
auto[1]	values[1]	values[5]	12	1			T64	2		T65	4		T316	1
auto[1]	values[1]	values[6]	9	1			T62	2		T233	2		T317	2
auto[1]	values[1]	values[7]	6	1			T100	3		T318	2		T319	1
auto[1]	values[2]	values[0]	13	1			T243	1		T320	6		T304	3
auto[1]	values[2]	values[1]	5	1			T253	2		T321	1		T322	2
auto[1]	values[2]	values[2]	13	1			T61	1		T237	1		T296	1
auto[1]	values[2]	values[3]	23	1			T47	1		T243	1		T323	2
auto[1]	values[2]	values[4]	14	1			T253	3		T82	1		T324	2
auto[1]	values[2]	values[5]	6	1			T275	1		T315	2		T325	3
auto[1]	values[2]	values[6]	10	1			T219	1		T302	3		T326	2
auto[1]	values[2]	values[7]	6	1			T68	1		T131	1		T327	1
auto[1]	values[3]	values[0]	14	1			T67	2		T270	2		T233	4
auto[1]	values[3]	values[1]	9	1			T67	2		T82	3		T328	2
auto[1]	values[3]	values[2]	11	1			T47	1		T217	1		T329	3
auto[1]	values[3]	values[3]	12	1			T221	1		T292	2		T277	2
auto[1]	values[3]	values[4]	4	1			T81	1		T82	1		T330	1
auto[1]	values[3]	values[6]	17	1			T69	2		T246	2		T233	1
auto[1]	values[3]	values[7]	8	1			T266	3		T304	2		T301	1
auto[1]	values[4]	values[0]	3	1			T331	3		-	-		-	-
auto[1]	values[4]	values[1]	4	1			T332	1		T333	1		T307	2
auto[1]	values[4]	values[2]	16	1			T60	2		T269	1		T270	2
auto[1]	values[4]	values[3]	9	1			T47	2		T296	1		T308	1
auto[1]	values[4]	values[4]	11	1			T237	1		T323	1		T266	2
auto[1]	values[4]	values[5]	8	1			T63	2		T237	2		T334	1
auto[1]	values[4]	values[6]	11	1			T321	1		T335	2		T336	1
auto[1]	values[4]	values[7]	12	1			T61	2		T36	1		T216	1
auto[1]	values[5]	values[0]	15	1			T53	1		T205	3		T270	2
auto[1]	values[5]	values[1]	7	1			T68	1		T221	2		T325	1
auto[1]	values[5]	values[2]	16	1			T233	1		T275	2		T337	1
auto[1]	values[5]	values[3]	5	1			T243	1		T322	1		T328	1
auto[1]	values[5]	values[4]	7	1			T233	2		T82	1		T322	2
auto[1]	values[5]	values[5]	9	1			T313	2		T320	1		T304	3
auto[1]	values[5]	values[6]	12	1			T66	2		T338	2		T339	1
auto[1]	values[5]	values[7]	11	1			T67	1		T253	1		T340	3
auto[1]	values[6]	values[0]	13	1			T216	1		T132	1		T275	3
auto[1]	values[6]	values[2]	6	1			T266	1		T305	2		T328	1
auto[1]	values[6]	values[3]	16	1			T266	3		T308	1		T311	2
auto[1]	values[6]	values[4]	6	1			T219	2		T311	1		T341	2
auto[1]	values[6]	values[5]	5	1			T329	2		T302	1		T342	2
auto[1]	values[6]	values[6]	11	1			T131	2		T287	2		T233	1
auto[1]	values[6]	values[7]	10	1			T243	1		T339	2		T343	2
auto[1]	values[7]	values[0]	9	1			T316	3		T311	2		T324	1
auto[1]	values[7]	values[1]	6	1			T68	2		T344	2		T345	2
auto[1]	values[7]	values[2]	10	1			T267	3		T341	5		T346	2
auto[1]	values[7]	values[3]	16	1			T47	5		T292	2		T275	2
auto[1]	values[7]	values[4]	10	1			T294	4		T337	2		T300	4
auto[1]	values[7]	values[5]	11	1			T237	1		T323	1		T270	1
auto[1]	values[7]	values[6]	9	1			T246	2		T233	4		T82	1
auto[1]	values[7]	values[7]	9	1			T304	3		T347	2		T348	2