Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	877	1			T8	10		T26	7		T35	14
all_values[1]	877	1			T8	10		T26	7		T35	14
all_values[2]	877	1			T8	10		T26	7		T35	14
all_values[3]	877	1			T8	10		T26	7		T35	14
all_values[4]	877	1			T8	10		T26	7		T35	14
all_values[5]	877	1			T8	10		T26	7		T35	14
all_values[6]	877	1			T8	10		T26	7		T35	14
all_values[7]	877	1			T8	10		T26	7		T35	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3730

1

T8

33

T26

22

T35

46

auto[1]

3286

1

T8

47

T26

34

T35

66

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2801

1

T8

32

T26

35

T35

46

auto[1]

4215

1

T8

48

T26

21

T35

66

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4049

1

T8

46

T26

38

T35

62

auto[1]

2967

1

T8

34

T26

18

T35

50

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	173	1			T26	1		T35	4		T36	1
all_values[0]	auto[0]	auto[0]	auto[1]	88	1			T8	4		T26	1		T36	2
all_values[0]	auto[0]	auto[1]	auto[0]	148	1			T8	1		T26	2		T35	5
all_values[0]	auto[0]	auto[1]	auto[1]	88	1			T8	1		T35	2		T36	2
all_values[0]	auto[1]	auto[0]	auto[1]	209	1			T8	3		T35	1		T36	2
all_values[0]	auto[1]	auto[1]	auto[1]	171	1			T8	1		T26	3		T35	2
all_values[1]	auto[0]	auto[0]	auto[0]	153	1			T8	1		T35	2		T36	2
all_values[1]	auto[0]	auto[0]	auto[1]	102	1			T8	2		T36	1		T37	2
all_values[1]	auto[0]	auto[1]	auto[0]	152	1			T8	1		T26	5		T35	3
all_values[1]	auto[0]	auto[1]	auto[1]	93	1			T8	1		T35	2		T37	3
all_values[1]	auto[1]	auto[0]	auto[1]	225	1			T26	2		T35	1		T36	1
all_values[1]	auto[1]	auto[1]	auto[1]	152	1			T8	5		T35	6		T36	2
all_values[2]	auto[0]	auto[0]	auto[0]	172	1			T8	3		T26	1		T35	4
all_values[2]	auto[0]	auto[0]	auto[1]	92	1			T35	1		T36	2		T203	2
all_values[2]	auto[0]	auto[1]	auto[0]	148	1			T8	3		T26	3		T35	3
all_values[2]	auto[0]	auto[1]	auto[1]	94	1			T36	1		T37	2		T203	2
all_values[2]	auto[1]	auto[0]	auto[1]	187	1			T35	1		T36	3		T37	6
all_values[2]	auto[1]	auto[1]	auto[1]	184	1			T8	4		T26	3		T35	5
all_values[3]	auto[0]	auto[0]	auto[0]	185	1			T8	2		T26	1		T36	4
all_values[3]	auto[0]	auto[0]	auto[1]	85	1			T8	1		T35	1		T37	1
all_values[3]	auto[0]	auto[1]	auto[0]	145	1			T26	1		T35	6		T37	3
all_values[3]	auto[0]	auto[1]	auto[1]	86	1			T8	1		T26	1		T35	1
all_values[3]	auto[1]	auto[0]	auto[1]	194	1			T8	1		T26	3		T35	3
all_values[3]	auto[1]	auto[1]	auto[1]	182	1			T8	5		T26	1		T35	3
all_values[4]	auto[0]	auto[0]	auto[0]	166	1			T26	2		T35	2		T36	2
all_values[4]	auto[0]	auto[0]	auto[1]	83	1			T35	1		T36	1		T37	2
all_values[4]	auto[0]	auto[1]	auto[0]	164	1			T8	4		T26	3		T35	3
all_values[4]	auto[0]	auto[1]	auto[1]	97	1			T8	1		T35	2		T36	2
all_values[4]	auto[1]	auto[0]	auto[1]	200	1			T8	3		T26	2		T35	2
all_values[4]	auto[1]	auto[1]	auto[1]	167	1			T8	2		T35	4		T36	2
all_values[5]	auto[0]	auto[0]	auto[0]	261	1			T8	1		T26	2		T35	4
all_values[5]	auto[0]	auto[1]	auto[0]	237	1			T8	6		T26	3		T35	4
all_values[5]	auto[1]	auto[0]	auto[1]	219	1			T8	1		T26	1		T35	3
all_values[5]	auto[1]	auto[1]	auto[1]	160	1			T8	2		T26	1		T35	3
all_values[6]	auto[0]	auto[0]	auto[0]	180	1			T8	2		T26	2		T35	3
all_values[6]	auto[0]	auto[0]	auto[1]	74	1			T35	1		T37	1		T203	1
all_values[6]	auto[0]	auto[1]	auto[0]	153	1			T8	2		T26	3		T36	1
all_values[6]	auto[0]	auto[1]	auto[1]	96	1			T8	1		T26	1		T35	2
all_values[6]	auto[1]	auto[0]	auto[1]	195	1			T8	5		T26	1		T35	4
all_values[6]	auto[1]	auto[1]	auto[1]	179	1			T35	4		T37	7		T203	1
all_values[7]	auto[0]	auto[0]	auto[0]	223	1			T8	2		T26	3		T35	2
all_values[7]	auto[0]	auto[0]	auto[1]	82	1			T8	2		T35	2		T36	1
all_values[7]	auto[0]	auto[1]	auto[0]	141	1			T8	4		T26	3		T35	1
all_values[7]	auto[0]	auto[1]	auto[1]	88	1			T35	1		T36	2		T37	2
all_values[7]	auto[1]	auto[0]	auto[1]	182	1			T35	4		T36	1		T37	5
all_values[7]	auto[1]	auto[1]	auto[1]	161	1			T8	2		T26	1		T35	4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal