Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1635

1

T13

7

T19

12

T27

6

auto[1]

1577

1

T4

2

T13

5

T19

13

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1723

1

T30

8

T41

14

T42

1

auto[1]

1489

1

T4

2

T13

12

T19

25

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2557

1

T4

2

T13

12

T19

25

auto[1]

655

1

T30

6

T41

9

T42

1

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	617	1			T13	2		T19	7		T29	5
valid[1]	652	1			T4	1		T13	1		T19	4
valid[2]	620	1			T13	4		T19	7		T27	3
valid[3]	671	1			T13	3		T19	4		T27	2
valid[4]	652	1			T4	1		T13	2		T19	3

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	104	1			T30	1		T41	1		T53	2
auto[0]	auto[0]	valid[0]	auto[1]	147	1			T13	1		T19	2		T29	2
auto[0]	auto[0]	valid[1]	auto[0]	110	1			T62	3		T123	1		T125	1
auto[0]	auto[0]	valid[1]	auto[1]	140	1			T19	2		T27	3		T29	5
auto[0]	auto[0]	valid[2]	auto[0]	97	1			T62	2		T98	1		T227	1
auto[0]	auto[0]	valid[2]	auto[1]	152	1			T13	3		T19	4		T27	1
auto[0]	auto[0]	valid[3]	auto[0]	128	1			T62	1		T123	2		T37	1
auto[0]	auto[0]	valid[3]	auto[1]	170	1			T13	1		T19	3		T27	2
auto[0]	auto[0]	valid[4]	auto[0]	106	1			T30	1		T41	2		T62	2
auto[0]	auto[0]	valid[4]	auto[1]	148	1			T13	2		T19	1		T30	1
auto[0]	auto[1]	valid[0]	auto[0]	97	1			T438	1		T37	1		T223	1
auto[0]	auto[1]	valid[0]	auto[1]	149	1			T13	1		T19	5		T29	3
auto[0]	auto[1]	valid[1]	auto[0]	104	1			T41	1		T62	2		T53	1
auto[0]	auto[1]	valid[1]	auto[1]	147	1			T4	1		T13	1		T19	2
auto[0]	auto[1]	valid[2]	auto[0]	112	1			T41	1		T62	1		T123	2
auto[0]	auto[1]	valid[2]	auto[1]	140	1			T13	1		T19	3		T27	2
auto[0]	auto[1]	valid[3]	auto[0]	119	1			T123	1		T125	1		T435	1
auto[0]	auto[1]	valid[3]	auto[1]	130	1			T13	2		T19	1		T29	1
auto[0]	auto[1]	valid[4]	auto[0]	91	1			T62	1		T123	1		T36	1
auto[0]	auto[1]	valid[4]	auto[1]	166	1			T4	1		T19	2		T126	1
auto[1]	auto[0]	valid[0]	auto[0]	72	1			T30	1		T41	2		T123	2
auto[1]	auto[0]	valid[1]	auto[0]	75	1			T30	1		T41	1		T62	1
auto[1]	auto[0]	valid[2]	auto[0]	55	1			T41	1		T62	1		T125	1
auto[1]	auto[0]	valid[3]	auto[0]	64	1			T30	2		T123	1		T435	1
auto[1]	auto[0]	valid[4]	auto[0]	67	1			T42	1		T62	2		T438	1
auto[1]	auto[1]	valid[0]	auto[0]	48	1			T30	2		T62	1		T123	1
auto[1]	auto[1]	valid[1]	auto[0]	76	1			T41	1		T62	2		T125	1
auto[1]	auto[1]	valid[2]	auto[0]	64	1			T41	2		T98	1		T224	1
auto[1]	auto[1]	valid[3]	auto[0]	60	1			T41	1		T227	2		T224	1
auto[1]	auto[1]	valid[4]	auto[0]	74	1			T41	1		T36	1		T125	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal