Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

43474

1

T5

3

T17

11

T28

7

auto[1]

15235

1

T4

2

T13

12

T19

381

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

42983

1

T4

2

T5

1

T13

12

auto[1]

15726

1

T5

2

T17

5

T28

4

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	30181	1			T4	2		T5	1		T13	12
others[1]	4947	1			T19	32		T29	21		T30	17
others[2]	4919	1			T5	1		T19	36		T28	1
others[3]	5532	1			T5	1		T17	2		T19	34
interest[1]	3279	1			T19	20		T29	14		T30	9
interest[4]	19801	1			T4	2		T13	12		T17	4
interest[64]	9851	1			T17	1		T19	61		T28	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	14133	1			T5	1		T17	5		T28	1
auto[0]	auto[0]	others[1]	2352	1			T30	6		T41	24		T62	13
auto[0]	auto[0]	others[2]	2328	1			T30	9		T41	12		T62	16
auto[0]	auto[0]	others[3]	2631	1			T28	1		T30	7		T41	23
auto[0]	auto[0]	interest[1]	1609	1			T30	3		T41	19		T62	10
auto[0]	auto[0]	interest[4]	9132	1			T17	3		T28	1		T30	36
auto[0]	auto[0]	interest[64]	4695	1			T17	1		T28	1		T30	18
auto[0]	auto[1]	others[0]	7947	1			T4	2		T13	12		T19	198
auto[0]	auto[1]	others[1]	1237	1			T19	32		T29	21		T30	2
auto[0]	auto[1]	others[2]	1296	1			T19	36		T29	20		T30	2
auto[0]	auto[1]	others[3]	1431	1			T19	34		T29	26		T30	2
auto[0]	auto[1]	interest[1]	806	1			T19	20		T29	14		T30	2
auto[0]	auto[1]	interest[4]	5375	1			T4	2		T13	12		T19	132
auto[0]	auto[1]	interest[64]	2518	1			T19	61		T29	41		T30	6
auto[1]	auto[0]	others[0]	8101	1			T17	3		T28	2		T30	34
auto[1]	auto[0]	others[1]	1358	1			T30	9		T41	11		T42	2
auto[1]	auto[0]	others[2]	1295	1			T5	1		T28	1		T30	5
auto[1]	auto[0]	others[3]	1470	1			T5	1		T17	2		T28	1
auto[1]	auto[0]	interest[1]	864	1			T30	4		T41	5		T62	6
auto[1]	auto[0]	interest[4]	5294	1			T17	1		T30	22		T31	1
auto[1]	auto[0]	interest[64]	2638	1			T30	11		T41	18		T42	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal