Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2607566	1			T1	1		T2	1		T3	1
all_values[1]	2607566	1			T1	1		T2	1		T3	1
all_values[2]	2607566	1			T1	1		T2	1		T3	1
all_values[3]	2607566	1			T1	1		T2	1		T3	1
all_values[4]	2607566	1			T1	1		T2	1		T3	1
all_values[5]	2607566	1			T1	1		T2	1		T3	1
all_values[6]	2607566	1			T1	1		T2	1		T3	1
all_values[7]	2607566	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20704773

1

T1

8

T2

8

T3

8

auto[1]

155755

1

T79

92

T20

164

T31

94

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20835203

1

T1

8

T2

8

T3

8

auto[1]

25325

1

T17

229

T79

71

T43

190

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2571961	1			T1	1		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	11555	1			T17	93		T79	6		T43	101
all_values[0]	auto[1]	auto[0]	23507	1			T79	7		T20	10		T31	10
all_values[0]	auto[1]	auto[1]	543	1			T79	3		T20	8		T31	4
all_values[1]	auto[0]	auto[0]	2590443	1			T1	1		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	7878	1			T17	83		T79	2		T43	89
all_values[1]	auto[1]	auto[0]	9025	1			T79	7		T20	6		T31	13
all_values[1]	auto[1]	auto[1]	220	1			T79	5		T20	10		T31	1
all_values[2]	auto[0]	auto[0]	2590238	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	2892	1			T17	53		T79	4		T20	5
all_values[2]	auto[1]	auto[0]	14193	1			T79	9		T20	20		T31	10
all_values[2]	auto[1]	auto[1]	243	1			T79	5		T20	7		T31	4
all_values[3]	auto[0]	auto[0]	2581485	1			T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	189	1			T79	4		T20	2		T31	5
all_values[3]	auto[1]	auto[0]	25678	1			T79	6		T20	22		T31	6
all_values[3]	auto[1]	auto[1]	214	1			T79	7		T20	4		T31	3
all_values[4]	auto[0]	auto[0]	2579819	1			T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	207	1			T20	7		T31	5		T33	3
all_values[4]	auto[1]	auto[0]	27357	1			T79	14		T20	10		T31	6
all_values[4]	auto[1]	auto[1]	183	1			T79	7		T20	6		T33	3
all_values[5]	auto[0]	auto[0]	2592089	1			T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	196	1			T79	6		T20	10		T31	5
all_values[5]	auto[1]	auto[0]	15101	1			T79	3		T20	13		T31	8
all_values[5]	auto[1]	auto[1]	180	1			T79	4		T20	3		T31	3
all_values[6]	auto[0]	auto[0]	2592102	1			T1	1		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	199	1			T79	7		T20	8		T31	4
all_values[6]	auto[1]	auto[0]	15077	1			T79	7		T20	12		T31	11
all_values[6]	auto[1]	auto[1]	188	1			T79	3		T20	9		T31	3
all_values[7]	auto[0]	auto[0]	2583290	1			T1	1		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	230	1			T79	6		T20	3		T31	2
all_values[7]	auto[1]	auto[0]	23838	1			T79	3		T20	18		T31	10
all_values[7]	auto[1]	auto[1]	208	1			T79	2		T20	6		T31	2