Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.06 98.38 94.01 98.62 89.36 97.19 95.57 99.26


Total tests in report: 1130
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
63.33 63.33 92.66 92.66 78.77 78.77 64.76 64.76 31.11 31.11 89.22 89.22 72.34 72.34 14.46 14.46 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_intercept.2746059100
82.49 19.16 97.42 4.76 90.45 11.68 88.58 23.82 86.67 55.56 95.92 6.70 84.92 12.59 33.47 19.01 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.3729279299
85.95 3.46 97.72 0.30 90.90 0.45 88.98 0.39 93.33 6.67 96.34 0.42 85.20 0.28 49.16 15.69 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_stress_all.2133302017
88.21 2.26 98.11 0.39 91.85 0.96 90.35 1.38 93.33 0.00 96.77 0.42 85.20 0.00 61.83 12.67 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_stress_all.1410471423
89.80 1.59 98.11 0.00 92.02 0.16 91.14 0.79 93.33 0.00 96.80 0.03 93.64 8.44 63.56 1.73 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3101930449
90.81 1.01 98.11 0.00 92.03 0.01 91.34 0.20 93.33 0.00 96.80 0.00 93.64 0.00 70.45 6.88 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_stress_all.2667278595
91.55 0.74 98.11 0.00 92.03 0.00 91.34 0.00 93.33 0.00 96.80 0.00 93.64 0.00 75.59 5.15 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.3316888656
92.23 0.68 98.13 0.02 92.03 0.00 96.06 4.72 93.33 0.00 96.80 0.00 93.64 0.00 75.59 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_ram_cfg.3284714323
92.72 0.49 98.13 0.00 92.04 0.01 96.06 0.00 93.33 0.00 96.80 0.00 93.64 0.00 79.01 3.42 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.3714167762
93.14 0.42 98.13 0.00 92.07 0.02 96.46 0.39 93.33 0.00 96.80 0.00 93.78 0.14 81.39 2.38 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_stress_all.793799751
93.48 0.35 98.14 0.01 92.13 0.06 98.43 1.97 93.33 0.00 96.82 0.02 93.91 0.14 81.63 0.25 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_sec_cm.2917987464
93.79 0.30 98.14 0.00 92.14 0.01 98.43 0.00 93.33 0.00 96.83 0.02 93.91 0.00 83.71 2.08 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_all.3228129967
94.08 0.29 98.14 0.00 92.14 0.00 98.43 0.00 93.33 0.00 96.83 0.00 93.91 0.00 85.74 2.03 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.1175684968
94.34 0.26 98.28 0.14 92.79 0.65 98.43 0.00 93.33 0.00 97.04 0.20 94.47 0.55 86.04 0.30 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode.3146807709
94.59 0.25 98.28 0.00 92.84 0.05 98.43 0.00 93.33 0.00 97.04 0.00 94.47 0.00 87.77 1.73 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_all.16614784
94.83 0.24 98.28 0.00 92.90 0.06 98.43 0.00 93.33 0.00 97.07 0.03 94.47 0.00 89.36 1.58 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.1989592719
95.00 0.17 98.29 0.01 93.01 0.11 98.43 0.00 93.33 0.00 97.09 0.02 94.47 0.00 90.40 1.04 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.865303404
95.16 0.16 98.29 0.00 93.01 0.00 98.43 0.00 93.33 0.00 97.09 0.00 94.47 0.00 91.53 1.14 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_stress_all.2720353333
95.31 0.15 98.32 0.03 93.04 0.02 98.43 0.00 93.33 0.00 97.14 0.05 94.61 0.14 92.33 0.79 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.1498899859
95.44 0.13 98.32 0.00 93.77 0.73 98.43 0.00 93.33 0.00 97.14 0.00 94.61 0.00 92.48 0.15 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.2876699624
95.56 0.12 98.32 0.00 93.77 0.00 98.43 0.00 93.33 0.00 97.14 0.00 95.44 0.83 92.48 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.2694216521
95.66 0.11 98.32 0.00 93.82 0.05 98.43 0.00 93.33 0.00 97.16 0.02 95.44 0.00 93.17 0.69 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.2031177663
95.77 0.11 98.32 0.00 93.82 0.00 98.43 0.00 93.33 0.00 97.16 0.00 95.44 0.00 93.91 0.74 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_mode_ignore_cmds.871401183
95.86 0.09 98.32 0.00 93.82 0.00 98.43 0.00 93.33 0.00 97.16 0.00 95.57 0.14 94.41 0.50 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_stress_all.2877601826
95.94 0.08 98.32 0.00 93.82 0.00 98.43 0.00 93.33 0.00 97.16 0.00 95.57 0.00 94.95 0.54 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.1867608671
96.01 0.07 98.32 0.00 93.82 0.00 98.43 0.00 93.33 0.00 97.16 0.00 95.57 0.00 95.45 0.50 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_and_tpm_min_idle.3896748805
96.08 0.07 98.32 0.00 93.83 0.01 98.43 0.00 93.33 0.00 97.16 0.00 95.57 0.00 95.89 0.45 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.3834402030
96.14 0.06 98.32 0.00 93.83 0.00 98.43 0.00 93.33 0.00 97.16 0.00 95.57 0.00 96.34 0.45 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_all.1674552518
96.20 0.06 98.32 0.00 93.83 0.00 98.43 0.00 93.33 0.00 97.16 0.00 95.57 0.00 96.73 0.40 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm.596660267
96.24 0.05 98.32 0.00 93.83 0.00 98.43 0.00 93.33 0.00 97.16 0.00 95.57 0.00 97.08 0.35 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.3185784797
96.29 0.04 98.32 0.00 93.83 0.00 98.43 0.00 93.33 0.00 97.16 0.00 95.57 0.00 97.38 0.30 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_all.4059694060
96.32 0.04 98.34 0.03 93.87 0.04 98.62 0.20 93.33 0.00 97.16 0.00 95.57 0.00 97.38 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_alert_test.1572494714
96.35 0.03 98.34 0.00 93.87 0.00 98.62 0.00 93.33 0.00 97.16 0.00 95.57 0.00 97.57 0.20 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.1564023790
96.38 0.03 98.34 0.00 93.87 0.00 98.62 0.00 93.33 0.00 97.16 0.00 95.57 0.00 97.77 0.20 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_all.2669634780
96.41 0.03 98.34 0.00 93.87 0.00 98.62 0.00 93.33 0.00 97.16 0.00 95.57 0.00 97.97 0.20 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.4169434454
96.43 0.02 98.38 0.04 93.87 0.00 98.62 0.00 93.33 0.00 97.19 0.03 95.57 0.00 98.07 0.10 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_mailbox.2918384899
96.46 0.02 98.38 0.00 93.88 0.01 98.62 0.00 93.33 0.00 97.19 0.00 95.57 0.00 98.22 0.15 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.1269740036
96.48 0.02 98.38 0.00 93.89 0.01 98.62 0.00 93.33 0.00 97.19 0.00 95.57 0.00 98.37 0.15 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_all.979923812
96.50 0.02 98.38 0.00 93.89 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.57 0.00 98.51 0.15 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_and_tpm.3776310170
96.52 0.01 98.38 0.00 93.89 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.57 0.00 98.61 0.10 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.35206638
96.53 0.01 98.38 0.00 93.89 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.57 0.00 98.71 0.10 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_mode.604904991
96.54 0.01 98.38 0.00 93.89 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.57 0.00 98.81 0.10 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_and_tpm.3404751287
96.56 0.01 98.38 0.00 93.89 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.57 0.00 98.91 0.10 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.3194664155
96.57 0.01 98.38 0.00 93.93 0.04 98.62 0.00 93.33 0.00 97.19 0.00 95.57 0.00 98.96 0.05 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_errors.3599998839
96.58 0.01 98.38 0.00 93.93 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.57 0.00 99.01 0.05 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.1491086667
96.58 0.01 98.38 0.00 93.93 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.57 0.00 99.06 0.05 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.3739432679
96.59 0.01 98.38 0.00 93.93 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.57 0.00 99.11 0.05 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode.3821521771
96.60 0.01 98.38 0.00 93.93 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.57 0.00 99.16 0.05 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode_ignore_cmds.3914789646
96.61 0.01 98.38 0.00 93.93 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.57 0.00 99.21 0.05 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_pass_addr_payload_swap.3679218793
96.61 0.01 98.38 0.00 93.93 0.00 98.62 0.00 93.33 0.00 97.19 0.00 95.57 0.00 99.26 0.05 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_mode.439924372
96.62 0.01 98.38 0.00 93.97 0.04 98.62 0.00 93.33 0.00 97.19 0.00 95.57 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.2599577093
96.62 0.01 98.38 0.00 93.99 0.02 98.62 0.00 93.33 0.00 97.19 0.00 95.57 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1215320783
96.62 0.01 98.38 0.00 94.01 0.01 98.62 0.00 93.33 0.00 97.19 0.00 95.57 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_csb_read.2840345585

Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3334662027
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3249596355
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4258475478
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.327876244
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.664150296
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.1488455684
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.380995252
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.4182711757
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.711366031
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.2090708769
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.4167392733
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2034662337
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.2660411133
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.2485616046
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.1185280266
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.576125226
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3694893348
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.4072222454
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.2966312166
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3915162997
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.1503702889
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.3236165797
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.447843937
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.2482713997
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.3563759949
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2187595474
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.867058979
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.3498727748
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.382280199
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.3209976623
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.1175703951
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3943529935
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.3193289413
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.2137994072
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3027594512
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/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_csb_read.1142964980
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/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_upload.2886057605



Total test records in report: 1130
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_csb_read.2840345585 Oct 03 03:54:26 AM UTC 24 Oct 03 03:54:28 AM UTC 24 14653607 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_ram_cfg.3284714323 Oct 03 03:54:29 AM UTC 24 Oct 03 03:54:32 AM UTC 24 16919047 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.1549446949 Oct 03 03:54:34 AM UTC 24 Oct 03 03:54:36 AM UTC 24 95344570 ps
T4 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_rw.2546067874 Oct 03 03:54:37 AM UTC 24 Oct 03 03:54:40 AM UTC 24 44288087 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.4074044932 Oct 03 03:54:40 AM UTC 24 Oct 03 03:54:47 AM UTC 24 786557724 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.2098638750 Oct 03 03:54:44 AM UTC 24 Oct 03 03:54:51 AM UTC 24 2923642458 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.35206638 Oct 03 03:54:31 AM UTC 24 Oct 03 03:54:57 AM UTC 24 18189847345 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_intercept.2746059100 Oct 03 03:54:47 AM UTC 24 Oct 03 03:54:58 AM UTC 24 2341415792 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_cfg_cmd.3837624004 Oct 03 03:55:00 AM UTC 24 Oct 03 03:55:04 AM UTC 24 155690563 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_upload.2463745791 Oct 03 03:54:59 AM UTC 24 Oct 03 03:55:09 AM UTC 24 2176307641 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_all.2917286215 Oct 03 03:54:33 AM UTC 24 Oct 03 03:55:14 AM UTC 24 1835457575 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_mailbox.2918384899 Oct 03 03:54:52 AM UTC 24 Oct 03 03:55:15 AM UTC 24 1599134350 ps
T13 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.252380795 Oct 03 03:55:15 AM UTC 24 Oct 03 03:55:39 AM UTC 24 4460965712 ps
T14 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode.3146807709 Oct 03 03:55:06 AM UTC 24 Oct 03 03:55:42 AM UTC 24 2010764260 ps
T15 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_all.3863146671 Oct 03 03:55:16 AM UTC 24 Oct 03 03:55:57 AM UTC 24 5810171300 ps
T16 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_sec_cm.2917987464 Oct 03 03:56:37 AM UTC 24 Oct 03 03:56:39 AM UTC 24 424447272 ps
T23 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_alert_test.1572494714 Oct 03 03:56:40 AM UTC 24 Oct 03 03:56:42 AM UTC 24 55251437 ps
T24 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_csb_read.3031086614 Oct 03 03:56:43 AM UTC 24 Oct 03 03:56:45 AM UTC 24 114473483 ps
T25 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.1209431459 Oct 03 03:57:05 AM UTC 24 Oct 03 03:57:08 AM UTC 24 258061567 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.3729279299 Oct 03 03:55:43 AM UTC 24 Oct 03 03:57:13 AM UTC 24 3684974914 ps
T26 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_rw.1229846812 Oct 03 03:57:09 AM UTC 24 Oct 03 03:57:13 AM UTC 24 642955735 ps
T27 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.627994059 Oct 03 03:56:49 AM UTC 24 Oct 03 03:57:18 AM UTC 24 13388347528 ps
T34 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.476207017 Oct 03 03:57:14 AM UTC 24 Oct 03 03:57:21 AM UTC 24 1421762212 ps
T35 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_intercept.2570030258 Oct 03 03:57:18 AM UTC 24 Oct 03 03:57:24 AM UTC 24 288157509 ps
T36 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.440665990 Oct 03 03:57:14 AM UTC 24 Oct 03 03:57:24 AM UTC 24 2804801065 ps
T356 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_cfg_cmd.2526302778 Oct 03 03:57:24 AM UTC 24 Oct 03 03:57:29 AM UTC 24 407310560 ps
T49 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_upload.3705971499 Oct 03 03:57:24 AM UTC 24 Oct 03 03:57:32 AM UTC 24 660020485 ps
T58 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_mailbox.4112192105 Oct 03 03:57:22 AM UTC 24 Oct 03 03:57:33 AM UTC 24 393325645 ps
T28 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_all.16614784 Oct 03 03:56:53 AM UTC 24 Oct 03 03:57:35 AM UTC 24 3247614791 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode.2962184264 Oct 03 03:57:29 AM UTC 24 Oct 03 03:57:41 AM UTC 24 323744628 ps
T79 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_stress_all.1701242555 Oct 03 03:57:42 AM UTC 24 Oct 03 03:57:45 AM UTC 24 43288938 ps
T45 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.3700753083 Oct 03 03:57:33 AM UTC 24 Oct 03 03:57:45 AM UTC 24 492622358 ps
T18 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_sec_cm.3540060058 Oct 03 03:57:45 AM UTC 24 Oct 03 03:57:48 AM UTC 24 83341439 ps
T81 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_alert_test.862069485 Oct 03 03:57:46 AM UTC 24 Oct 03 03:57:49 AM UTC 24 27419086 ps
T357 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_intercept.2572882457 Oct 03 04:00:49 AM UTC 24 Oct 03 04:00:53 AM UTC 24 105426336 ps
T358 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_csb_read.1616611824 Oct 03 03:57:50 AM UTC 24 Oct 03 03:57:52 AM UTC 24 18720996 ps
T29 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.3936771582 Oct 03 03:57:53 AM UTC 24 Oct 03 03:58:01 AM UTC 24 569231425 ps
T95 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.763501112 Oct 03 03:58:00 AM UTC 24 Oct 03 03:58:03 AM UTC 24 200540786 ps
T41 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_rw.168433308 Oct 03 03:58:02 AM UTC 24 Oct 03 03:58:06 AM UTC 24 87405361 ps
T50 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.3969620803 Oct 03 03:58:03 AM UTC 24 Oct 03 03:58:15 AM UTC 24 241064190 ps
T46 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.1376665475 Oct 03 03:55:10 AM UTC 24 Oct 03 03:58:16 AM UTC 24 72073680198 ps
T359 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_upload.479614046 Oct 03 03:58:18 AM UTC 24 Oct 03 03:58:22 AM UTC 24 91189167 ps
T51 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.9693670 Oct 03 03:58:06 AM UTC 24 Oct 03 03:58:24 AM UTC 24 6210589629 ps
T80 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_cfg_cmd.4240995380 Oct 03 03:58:23 AM UTC 24 Oct 03 03:58:33 AM UTC 24 419671468 ps
T100 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_intercept.1754516654 Oct 03 03:58:16 AM UTC 24 Oct 03 03:58:38 AM UTC 24 1910921510 ps
T78 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.34790705 Oct 03 03:58:39 AM UTC 24 Oct 03 03:58:46 AM UTC 24 92408826 ps
T42 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_all.3418622315 Oct 03 03:57:53 AM UTC 24 Oct 03 03:58:46 AM UTC 24 8275412757 ps
T227 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_mailbox.580161591 Oct 03 03:58:16 AM UTC 24 Oct 03 03:58:47 AM UTC 24 1260625807 ps
T43 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.2497420353 Oct 03 03:57:36 AM UTC 24 Oct 03 03:58:56 AM UTC 24 8496638152 ps
T117 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode.1416809178 Oct 03 03:58:25 AM UTC 24 Oct 03 03:58:57 AM UTC 24 2720737813 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_sec_cm.313259123 Oct 03 03:58:58 AM UTC 24 Oct 03 03:59:00 AM UTC 24 123838331 ps
T82 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_alert_test.713458342 Oct 03 03:59:01 AM UTC 24 Oct 03 03:59:03 AM UTC 24 26787732 ps
T360 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_csb_read.1844465612 Oct 03 03:59:04 AM UTC 24 Oct 03 03:59:06 AM UTC 24 16925616 ps
T44 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.1821345034 Oct 03 03:58:48 AM UTC 24 Oct 03 03:59:14 AM UTC 24 3957657251 ps
T59 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_all.1563748641 Oct 03 03:59:13 AM UTC 24 Oct 03 03:59:16 AM UTC 24 594344725 ps
T361 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.2532941349 Oct 03 03:59:15 AM UTC 24 Oct 03 03:59:18 AM UTC 24 46719085 ps
T77 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_rw.1017129100 Oct 03 03:59:17 AM UTC 24 Oct 03 03:59:19 AM UTC 24 16317993 ps
T362 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.1768742143 Oct 03 03:59:10 AM UTC 24 Oct 03 03:59:30 AM UTC 24 9332569295 ps
T52 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.2565532692 Oct 03 03:59:20 AM UTC 24 Oct 03 03:59:33 AM UTC 24 462839772 ps
T118 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.4102556340 Oct 03 03:59:18 AM UTC 24 Oct 03 03:59:35 AM UTC 24 2641699570 ps
T39 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_all.3793453916 Oct 03 03:58:47 AM UTC 24 Oct 03 03:59:38 AM UTC 24 2534200279 ps
T213 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_mailbox.2267945211 Oct 03 03:59:35 AM UTC 24 Oct 03 03:59:38 AM UTC 24 63861920 ps
T101 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_intercept.1390398044 Oct 03 03:59:32 AM UTC 24 Oct 03 03:59:43 AM UTC 24 604643318 ps
T224 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_upload.1194713232 Oct 03 03:59:36 AM UTC 24 Oct 03 03:59:43 AM UTC 24 624129505 ps
T96 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_cfg_cmd.30055732 Oct 03 03:59:39 AM UTC 24 Oct 03 03:59:43 AM UTC 24 369952169 ps
T145 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode.2091797253 Oct 03 03:59:39 AM UTC 24 Oct 03 03:59:48 AM UTC 24 201052517 ps
T146 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.694492280 Oct 03 03:59:44 AM UTC 24 Oct 03 03:59:50 AM UTC 24 223755355 ps
T40 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.2031177663 Oct 03 03:57:30 AM UTC 24 Oct 03 03:59:50 AM UTC 24 12621026615 ps
T20 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_stress_all.786237481 Oct 03 03:59:51 AM UTC 24 Oct 03 04:00:14 AM UTC 24 4379349452 ps
T21 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_sec_cm.1898942396 Oct 03 04:00:15 AM UTC 24 Oct 03 04:00:18 AM UTC 24 560053336 ps
T363 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_alert_test.3404278122 Oct 03 04:00:19 AM UTC 24 Oct 03 04:00:21 AM UTC 24 43357647 ps
T364 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_csb_read.1897715956 Oct 03 04:00:22 AM UTC 24 Oct 03 04:00:24 AM UTC 24 13836328 ps
T365 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.2095328140 Oct 03 04:00:28 AM UTC 24 Oct 03 04:00:40 AM UTC 24 777085556 ps
T72 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.1942793238 Oct 03 03:59:44 AM UTC 24 Oct 03 04:00:41 AM UTC 24 15359162409 ps
T366 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.2508761429 Oct 03 04:00:41 AM UTC 24 Oct 03 04:00:44 AM UTC 24 133302847 ps
T331 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_all.1110806306 Oct 03 04:00:28 AM UTC 24 Oct 03 04:00:46 AM UTC 24 1070608237 ps
T352 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_rw.2835666362 Oct 03 04:00:42 AM UTC 24 Oct 03 04:00:48 AM UTC 24 466799012 ps
T367 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_mailbox.2486424581 Oct 03 04:00:51 AM UTC 24 Oct 03 04:00:55 AM UTC 24 67190445 ps
T73 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.1491086667 Oct 03 03:57:34 AM UTC 24 Oct 03 04:00:59 AM UTC 24 49031313944 ps
T54 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.297532886 Oct 03 04:00:47 AM UTC 24 Oct 03 04:01:02 AM UTC 24 1099721284 ps
T97 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_cfg_cmd.3457535386 Oct 03 04:00:56 AM UTC 24 Oct 03 04:01:03 AM UTC 24 789355414 ps
T147 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.426735167 Oct 03 04:01:02 AM UTC 24 Oct 03 04:01:09 AM UTC 24 221557462 ps
T74 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.3185784797 Oct 03 03:59:49 AM UTC 24 Oct 03 04:01:10 AM UTC 24 14341007959 ps
T368 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode.2559683989 Oct 03 04:01:00 AM UTC 24 Oct 03 04:01:12 AM UTC 24 1408126159 ps
T47 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.2095443357 Oct 03 04:00:44 AM UTC 24 Oct 03 04:01:17 AM UTC 24 12678204339 ps
T75 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_upload.1165212546 Oct 03 04:00:55 AM UTC 24 Oct 03 04:01:20 AM UTC 24 3328754175 ps
T22 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_sec_cm.1146142350 Oct 03 04:01:18 AM UTC 24 Oct 03 04:01:21 AM UTC 24 33580096 ps
T76 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.3945052151 Oct 03 03:58:47 AM UTC 24 Oct 03 04:01:22 AM UTC 24 14374126095 ps
T369 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_alert_test.2659705812 Oct 03 04:01:21 AM UTC 24 Oct 03 04:01:23 AM UTC 24 13694167 ps
T370 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_csb_read.24636102 Oct 03 04:01:21 AM UTC 24 Oct 03 04:01:23 AM UTC 24 101590307 ps
T371 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.2947131006 Oct 03 04:01:26 AM UTC 24 Oct 03 04:01:29 AM UTC 24 43775979 ps
T372 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.2611158129 Oct 03 04:01:24 AM UTC 24 Oct 03 04:01:29 AM UTC 24 1007565014 ps
T30 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_stress_all.2133302017 Oct 03 03:58:56 AM UTC 24 Oct 03 04:01:30 AM UTC 24 5775693493 ps
T351 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_rw.1621042000 Oct 03 04:01:29 AM UTC 24 Oct 03 04:01:33 AM UTC 24 39108365 ps
T232 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_intercept.3664158859 Oct 03 04:01:34 AM UTC 24 Oct 03 04:01:38 AM UTC 24 105391221 ps
T244 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.2541004485 Oct 03 04:01:32 AM UTC 24 Oct 03 04:01:49 AM UTC 24 2245915249 ps
T340 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_all.979923812 Oct 03 04:01:24 AM UTC 24 Oct 03 04:01:52 AM UTC 24 5862731657 ps
T53 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_all.3228129967 Oct 03 03:59:44 AM UTC 24 Oct 03 04:01:53 AM UTC 24 5736839345 ps
T207 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.374675538 Oct 03 04:01:29 AM UTC 24 Oct 03 04:01:53 AM UTC 24 7245276335 ps
T373 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_upload.3456984987 Oct 03 04:01:50 AM UTC 24 Oct 03 04:01:54 AM UTC 24 153831882 ps
T264 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_cfg_cmd.2888144252 Oct 03 04:01:53 AM UTC 24 Oct 03 04:01:58 AM UTC 24 110633933 ps
T89 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_all.961734978 Oct 03 04:01:03 AM UTC 24 Oct 03 04:02:01 AM UTC 24 6310961365 ps
T148 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.1378522516 Oct 03 04:01:55 AM UTC 24 Oct 03 04:02:15 AM UTC 24 767836595 ps
T149 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode.3122708703 Oct 03 04:01:54 AM UTC 24 Oct 03 04:02:16 AM UTC 24 834612915 ps
T268 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_mailbox.3665414868 Oct 03 04:01:40 AM UTC 24 Oct 03 04:02:18 AM UTC 24 7023141139 ps
T374 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_alert_test.2182166495 Oct 03 04:02:17 AM UTC 24 Oct 03 04:02:19 AM UTC 24 16865028 ps
T375 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_csb_read.896891580 Oct 03 04:02:19 AM UTC 24 Oct 03 04:02:21 AM UTC 24 15185756 ps
T376 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.3288457154 Oct 03 04:02:23 AM UTC 24 Oct 03 04:02:26 AM UTC 24 552000900 ps
T354 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_rw.342113716 Oct 03 04:02:26 AM UTC 24 Oct 03 04:02:29 AM UTC 24 24471285 ps
T377 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.1245196471 Oct 03 04:02:22 AM UTC 24 Oct 03 04:02:33 AM UTC 24 4073700930 ps
T335 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_all.4208296256 Oct 03 04:02:22 AM UTC 24 Oct 03 04:02:39 AM UTC 24 4647213591 ps
T37 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.455982852 Oct 03 04:02:01 AM UTC 24 Oct 03 04:02:40 AM UTC 24 1920954040 ps
T55 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.1867608671 Oct 03 04:01:00 AM UTC 24 Oct 03 04:02:42 AM UTC 24 16737510381 ps
T208 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_upload.1413698312 Oct 03 04:02:41 AM UTC 24 Oct 03 04:02:46 AM UTC 24 374980054 ps
T238 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.1078816794 Oct 03 04:02:30 AM UTC 24 Oct 03 04:02:48 AM UTC 24 16615050568 ps
T254 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_cfg_cmd.2193197627 Oct 03 04:02:43 AM UTC 24 Oct 03 04:02:50 AM UTC 24 847541027 ps
T378 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_intercept.3804388329 Oct 03 04:02:40 AM UTC 24 Oct 03 04:02:52 AM UTC 24 595637105 ps
T240 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode.108726534 Oct 03 04:02:47 AM UTC 24 Oct 03 04:02:53 AM UTC 24 189681742 ps
T219 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.1291441682 Oct 03 04:02:34 AM UTC 24 Oct 03 04:03:01 AM UTC 24 6282739800 ps
T150 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.3633786270 Oct 03 04:02:51 AM UTC 24 Oct 03 04:03:02 AM UTC 24 1650024328 ps
T31 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_stress_all.30880927 Oct 03 04:02:16 AM UTC 24 Oct 03 04:03:29 AM UTC 24 18252438431 ps
T167 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_alert_test.1621197545 Oct 03 04:03:30 AM UTC 24 Oct 03 04:03:32 AM UTC 24 11588975 ps
T168 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_csb_read.440311330 Oct 03 04:03:33 AM UTC 24 Oct 03 04:03:35 AM UTC 24 13290820 ps
T56 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_all.1674552518 Oct 03 03:57:34 AM UTC 24 Oct 03 04:03:40 AM UTC 24 30189501827 ps
T57 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.1564023790 Oct 03 03:58:34 AM UTC 24 Oct 03 04:03:44 AM UTC 24 143421297204 ps
T169 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.1964415410 Oct 03 04:03:44 AM UTC 24 Oct 03 04:03:47 AM UTC 24 87730268 ps
T170 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_all.1741871448 Oct 03 04:03:40 AM UTC 24 Oct 03 04:03:50 AM UTC 24 1686834046 ps
T171 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_rw.1687572424 Oct 03 04:03:48 AM UTC 24 Oct 03 04:03:50 AM UTC 24 122391841 ps
T172 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.2181950907 Oct 03 04:03:39 AM UTC 24 Oct 03 04:03:59 AM UTC 24 17911006400 ps
T173 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_mailbox.3748165533 Oct 03 04:02:40 AM UTC 24 Oct 03 04:04:02 AM UTC 24 9917165771 ps
T178 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.4175972277 Oct 03 04:03:51 AM UTC 24 Oct 03 04:04:04 AM UTC 24 2237655229 ps
T294 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.4266335578 Oct 03 04:03:51 AM UTC 24 Oct 03 04:04:05 AM UTC 24 11668028902 ps
T379 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_cfg_cmd.2116629743 Oct 03 04:04:06 AM UTC 24 Oct 03 04:04:10 AM UTC 24 32382507 ps
T380 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_intercept.2470556067 Oct 03 04:04:01 AM UTC 24 Oct 03 04:04:11 AM UTC 24 277167184 ps
T265 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_upload.3321907845 Oct 03 04:04:05 AM UTC 24 Oct 03 04:04:15 AM UTC 24 866624276 ps
T177 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.446484530 Oct 03 04:01:54 AM UTC 24 Oct 03 04:04:16 AM UTC 24 15605468948 ps
T381 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode.3996617796 Oct 03 04:04:11 AM UTC 24 Oct 03 04:04:18 AM UTC 24 109843805 ps
T382 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.1845360268 Oct 03 04:04:15 AM UTC 24 Oct 03 04:04:25 AM UTC 24 1041005995 ps
T269 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_mailbox.2071120231 Oct 03 04:04:03 AM UTC 24 Oct 03 04:04:30 AM UTC 24 1719410441 ps
T32 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_stress_all.3497199815 Oct 03 04:03:03 AM UTC 24 Oct 03 04:04:32 AM UTC 24 6683421505 ps
T383 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_alert_test.3988861738 Oct 03 04:04:33 AM UTC 24 Oct 03 04:04:35 AM UTC 24 14997582 ps
T384 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_csb_read.1142964980 Oct 03 04:04:36 AM UTC 24 Oct 03 04:04:38 AM UTC 24 17189468 ps
T90 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.2756566633 Oct 03 03:55:39 AM UTC 24 Oct 03 04:04:53 AM UTC 24 53916433825 ps
T247 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.3834402030 Oct 03 04:02:09 AM UTC 24 Oct 03 04:04:54 AM UTC 24 47120187435 ps
T210 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.1795246480 Oct 03 04:03:02 AM UTC 24 Oct 03 04:04:55 AM UTC 24 11215328785 ps
T385 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.692938799 Oct 03 04:04:54 AM UTC 24 Oct 03 04:04:57 AM UTC 24 59137185 ps
T86 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.1498899859 Oct 03 04:01:11 AM UTC 24 Oct 03 04:05:00 AM UTC 24 52018752097 ps
T131 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_rw.75179868 Oct 03 04:04:56 AM UTC 24 Oct 03 04:05:08 AM UTC 24 159114640 ps
T132 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.42749897 Oct 03 04:04:42 AM UTC 24 Oct 03 04:05:10 AM UTC 24 3803587256 ps
T133 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.4098195731 Oct 03 04:05:01 AM UTC 24 Oct 03 04:05:12 AM UTC 24 252676118 ps
T134 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.3586121066 Oct 03 04:04:58 AM UTC 24 Oct 03 04:05:14 AM UTC 24 381728400 ps
T135 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.3714167762 Oct 03 04:02:54 AM UTC 24 Oct 03 04:05:14 AM UTC 24 12533155517 ps
T136 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_cfg_cmd.2826702118 Oct 03 04:05:11 AM UTC 24 Oct 03 04:05:15 AM UTC 24 110454628 ps
T137 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.1382921007 Oct 03 04:04:18 AM UTC 24 Oct 03 04:05:17 AM UTC 24 3130511064 ps
T138 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_mailbox.3278105289 Oct 03 04:05:09 AM UTC 24 Oct 03 04:05:19 AM UTC 24 725722596 ps
T139 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.138473445 Oct 03 04:05:15 AM UTC 24 Oct 03 04:05:23 AM UTC 24 130340401 ps
T203 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.997816817 Oct 03 03:59:50 AM UTC 24 Oct 03 04:05:27 AM UTC 24 29478825586 ps
T337 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_all.1302181612 Oct 03 04:04:54 AM UTC 24 Oct 03 04:05:27 AM UTC 24 4359986263 ps
T386 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_alert_test.906080029 Oct 03 04:05:28 AM UTC 24 Oct 03 04:05:30 AM UTC 24 34831680 ps
T387 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_csb_read.2332248331 Oct 03 04:05:28 AM UTC 24 Oct 03 04:05:30 AM UTC 24 48642316 ps
T336 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_all.2999496458 Oct 03 04:07:36 AM UTC 24 Oct 03 04:07:55 AM UTC 24 1831338853 ps
T324 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode.3019891581 Oct 03 04:05:13 AM UTC 24 Oct 03 04:05:33 AM UTC 24 3390062167 ps
T98 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.1989592719 Oct 03 04:02:49 AM UTC 24 Oct 03 04:05:36 AM UTC 24 9101379800 ps
T388 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.1327678407 Oct 03 04:05:34 AM UTC 24 Oct 03 04:05:37 AM UTC 24 82132012 ps
T233 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_upload.517967860 Oct 03 04:05:11 AM UTC 24 Oct 03 04:05:41 AM UTC 24 12006666333 ps
T341 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_rw.547538680 Oct 03 04:05:38 AM UTC 24 Oct 03 04:05:42 AM UTC 24 113532786 ps
T266 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.2903328095 Oct 03 04:05:38 AM UTC 24 Oct 03 04:05:43 AM UTC 24 75029675 ps
T200 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.2161973493 Oct 03 04:04:12 AM UTC 24 Oct 03 04:05:43 AM UTC 24 5260965684 ps
T293 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_intercept.1232732697 Oct 03 04:05:04 AM UTC 24 Oct 03 04:05:43 AM UTC 24 13343569587 ps
T389 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_intercept.2031856791 Oct 03 04:05:43 AM UTC 24 Oct 03 04:05:47 AM UTC 24 302149787 ps
T390 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_mailbox.1814545535 Oct 03 04:05:44 AM UTC 24 Oct 03 04:05:49 AM UTC 24 53872977 ps
T255 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_cfg_cmd.3568337035 Oct 03 04:05:44 AM UTC 24 Oct 03 04:05:49 AM UTC 24 92706856 ps
T289 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_upload.2886057605 Oct 03 04:05:44 AM UTC 24 Oct 03 04:05:51 AM UTC 24 5239219877 ps
T391 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.530839360 Oct 03 04:05:31 AM UTC 24 Oct 03 04:05:52 AM UTC 24 27693346353 ps
T295 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.2608991550 Oct 03 04:05:42 AM UTC 24 Oct 03 04:05:52 AM UTC 24 3491695130 ps
T223 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode.583304855 Oct 03 04:05:48 AM UTC 24 Oct 03 04:05:56 AM UTC 24 163274845 ps
T33 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_stress_all.2334326372 Oct 03 04:05:54 AM UTC 24 Oct 03 04:05:57 AM UTC 24 51708107 ps
T99 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.356158198 Oct 03 04:05:50 AM UTC 24 Oct 03 04:05:57 AM UTC 24 289270096 ps
T392 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_alert_test.854656187 Oct 03 04:05:57 AM UTC 24 Oct 03 04:05:59 AM UTC 24 79474291 ps
T393 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_all.1037245879 Oct 03 04:07:51 AM UTC 24 Oct 03 04:07:53 AM UTC 24 12557643 ps
T394 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_csb_read.3185363576 Oct 03 04:05:58 AM UTC 24 Oct 03 04:06:00 AM UTC 24 51375401 ps
T395 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.2376979679 Oct 03 04:06:01 AM UTC 24 Oct 03 04:06:03 AM UTC 24 68030812 ps
T332 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.246358482 Oct 03 04:04:26 AM UTC 24 Oct 03 04:06:04 AM UTC 24 20655127420 ps
T396 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.2563741602 Oct 03 04:06:00 AM UTC 24 Oct 03 04:06:04 AM UTC 24 409484481 ps
T397 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_rw.1991745318 Oct 03 04:06:04 AM UTC 24 Oct 03 04:06:06 AM UTC 24 37775480 ps
T398 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.3207144616 Oct 03 04:06:06 AM UTC 24 Oct 03 04:06:09 AM UTC 24 233516837 ps
T220 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_all.4180890448 Oct 03 04:05:17 AM UTC 24 Oct 03 04:06:13 AM UTC 24 9446020543 ps
T201 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.3439826586 Oct 03 04:06:06 AM UTC 24 Oct 03 04:06:13 AM UTC 24 2930330991 ps
T184 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.1732307381 Oct 03 04:05:49 AM UTC 24 Oct 03 04:06:19 AM UTC 24 1653868404 ps
T258 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_intercept.1555630030 Oct 03 04:06:08 AM UTC 24 Oct 03 04:06:19 AM UTC 24 317536501 ps
T399 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_cfg_cmd.3730945374 Oct 03 04:06:14 AM UTC 24 Oct 03 04:06:23 AM UTC 24 351927788 ps
T190 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_upload.107886333 Oct 03 04:06:10 AM UTC 24 Oct 03 04:06:25 AM UTC 24 3676773483 ps
T286 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_mailbox.2907466353 Oct 03 04:06:10 AM UTC 24 Oct 03 04:06:30 AM UTC 24 502321563 ps
T339 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_all.3511395644 Oct 03 04:05:34 AM UTC 24 Oct 03 04:06:30 AM UTC 24 15589859838 ps
T400 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.2322012648 Oct 03 04:06:20 AM UTC 24 Oct 03 04:06:34 AM UTC 24 3558723624 ps
T401 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_alert_test.3035315125 Oct 03 04:06:35 AM UTC 24 Oct 03 04:06:37 AM UTC 24 103047156 ps
T402 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_csb_read.2876055987 Oct 03 04:06:38 AM UTC 24 Oct 03 04:06:40 AM UTC 24 19451249 ps
T327 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode.1229478446 Oct 03 04:06:14 AM UTC 24 Oct 03 04:06:45 AM UTC 24 1765438821 ps
T334 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_all.1149112375 Oct 03 04:06:01 AM UTC 24 Oct 03 04:07:02 AM UTC 24 32111402944 ps
T403 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.1628419570 Oct 03 04:07:02 AM UTC 24 Oct 03 04:07:04 AM UTC 24 29205001 ps
T404 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_rw.2946425964 Oct 03 04:07:06 AM UTC 24 Oct 03 04:07:08 AM UTC 24 17463262 ps
T231 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_all.3006663011 Oct 03 04:06:23 AM UTC 24 Oct 03 04:07:13 AM UTC 24 1857022785 ps
T246 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.2376741579 Oct 03 04:05:54 AM UTC 24 Oct 03 04:07:15 AM UTC 24 5282202025 ps
T405 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.3227042068 Oct 03 04:06:44 AM UTC 24 Oct 03 04:07:17 AM UTC 24 4855738262 ps
T406 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_mailbox.3839439176 Oct 03 04:07:15 AM UTC 24 Oct 03 04:07:20 AM UTC 24 432528150 ps
T407 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.1877600204 Oct 03 04:06:27 AM UTC 24 Oct 03 04:07:22 AM UTC 24 2884727102 ps
T282 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.3088283803 Oct 03 04:07:10 AM UTC 24 Oct 03 04:07:22 AM UTC 24 952549434 ps
T217 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_intercept.1651463007 Oct 03 04:07:14 AM UTC 24 Oct 03 04:07:24 AM UTC 24 771151217 ps
T408 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_alert_test.926216269 Oct 03 04:07:56 AM UTC 24 Oct 03 04:07:58 AM UTC 24 17521663 ps
T409 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_upload.1032825197 Oct 03 04:07:17 AM UTC 24 Oct 03 04:07:24 AM UTC 24 5916087412 ps
T291 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_cfg_cmd.1046865795 Oct 03 04:07:21 AM UTC 24 Oct 03 04:07:29 AM UTC 24 253230670 ps
T410 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.3177016866 Oct 03 04:07:25 AM UTC 24 Oct 03 04:07:31 AM UTC 24 650034995 ps
T325 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode.3821521771 Oct 03 04:07:22 AM UTC 24 Oct 03 04:07:32 AM UTC 24 364284558 ps
T333 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_all.2325391663 Oct 03 04:06:45 AM UTC 24 Oct 03 04:07:32 AM UTC 24 22499203566 ps
T176 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_stress_all.1410471423 Oct 03 04:06:32 AM UTC 24 Oct 03 04:07:34 AM UTC 24 11830534504 ps
T218 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.3739432679 Oct 03 04:06:19 AM UTC 24 Oct 03 04:07:34 AM UTC 24 16032178993 ps
T187 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_all.3236776340 Oct 03 04:07:26 AM UTC 24 Oct 03 04:07:35 AM UTC 24 178487678 ps
T411 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_alert_test.1806393782 Oct 03 04:07:33 AM UTC 24 Oct 03 04:07:35 AM UTC 24 16508210 ps
T158 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_stress_all.8369118 Oct 03 04:01:13 AM UTC 24 Oct 03 04:07:36 AM UTC 24 138209412869 ps
T257 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_mailbox.1618697362 Oct 03 04:07:42 AM UTC 24 Oct 03 04:07:57 AM UTC 24 1459227136 ps
T412 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_csb_read.342269032 Oct 03 04:07:35 AM UTC 24 Oct 03 04:07:38 AM UTC 24 20481577 ps
T413 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.3324545602 Oct 03 04:07:36 AM UTC 24 Oct 03 04:07:39 AM UTC 24 26461126 ps
T194 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.3316888656 Oct 03 04:05:20 AM UTC 24 Oct 03 04:07:39 AM UTC 24 41524342531 ps
T353 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_rw.2524348915 Oct 03 04:07:39 AM UTC 24 Oct 03 04:07:41 AM UTC 24 90321942 ps
T262 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.230782387 Oct 03 04:07:39 AM UTC 24 Oct 03 04:07:45 AM UTC 24 528179826 ps
T414 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode_ignore_cmds.3760892350 Oct 03 04:07:22 AM UTC 24 Oct 03 04:07:45 AM UTC 24 1201275704 ps
T229 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.375376186 Oct 03 04:07:09 AM UTC 24 Oct 03 04:07:45 AM UTC 24 31079180165 ps
T415 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_upload.3139114063 Oct 03 04:07:46 AM UTC 24 Oct 03 04:07:50 AM UTC 24 540779673 ps
T159 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_stress_all.793799751 Oct 03 04:04:31 AM UTC 24 Oct 03 04:07:51 AM UTC 24 12133934021 ps
T416 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_intercept.986008296 Oct 03 04:07:40 AM UTC 24 Oct 03 04:07:51 AM UTC 24 533527356 ps
T259 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_cfg_cmd.112193816 Oct 03 04:07:46 AM UTC 24 Oct 03 04:07:52 AM UTC 24 355762243 ps
T342 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.2176972244 Oct 03 04:06:31 AM UTC 24 Oct 03 04:07:52 AM UTC 24 7770184490 ps
T417 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.382239696 Oct 03 04:07:35 AM UTC 24 Oct 03 04:07:55 AM UTC 24 4692049149 ps
T348 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.1205046234 Oct 03 04:07:52 AM UTC 24 Oct 03 04:07:56 AM UTC 24 208225842 ps
T215 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.209646518 Oct 03 04:07:40 AM UTC 24 Oct 03 04:07:57 AM UTC 24 3232769239 ps
T418 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_csb_read.3884514187 Oct 03 04:07:57 AM UTC 24 Oct 03 04:07:59 AM UTC 24 78154644 ps
T419 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_rw.3380307859 Oct 03 04:07:59 AM UTC 24 Oct 03 04:08:01 AM UTC 24 19594902 ps
T420 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.83144858 Oct 03 04:07:59 AM UTC 24 Oct 03 04:08:02 AM UTC 24 128247585 ps
T421 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.887444282 Oct 03 04:07:51 AM UTC 24 Oct 03 04:08:03 AM UTC 24 784835956 ps
T422 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.398684742 Oct 03 04:07:58 AM UTC 24 Oct 03 04:08:05 AM UTC 24 1370814783 ps
T209 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_upload.3224596203 Oct 03 04:08:06 AM UTC 24 Oct 03 04:08:10 AM UTC 24 290877201 ps
T423 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_intercept.3427942883 Oct 03 04:08:02 AM UTC 24 Oct 03 04:08:10 AM UTC 24 876426379 ps
T424 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_mailbox.297472325 Oct 03 04:08:03 AM UTC 24 Oct 03 04:08:13 AM UTC 24 626838786 ps
T195 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_all.2769257504 Oct 03 04:04:16 AM UTC 24 Oct 03 04:08:13 AM UTC 24 24271420327 ps
T279 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.2893739926 Oct 03 04:08:02 AM UTC 24 Oct 03 04:08:19 AM UTC 24 12646215603 ps
T261 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_cfg_cmd.2809542697 Oct 03 04:08:11 AM UTC 24 Oct 03 04:08:20 AM UTC 24 2207870431 ps
T87 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.3856429386 Oct 03 04:05:52 AM UTC 24 Oct 03 04:08:22 AM UTC 24 28467059129 ps
T425 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_read_buffer_direct.194526841 Oct 03 04:08:15 AM UTC 24 Oct 03 04:08:27 AM UTC 24 1297118594 ps
T160 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_stress_all.2771191054 Oct 03 04:08:28 AM UTC 24 Oct 03 04:08:30 AM UTC 24 216361641 ps
T426 /workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_alert_test.11308972 Oct 03 04:08:31 AM UTC 24 Oct 03 04:08:33 AM UTC 24 46036018 ps