Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	36757	1			T6	2		T8	2		T9	2
auto[SpiFlashAddrCfg]	7639	1			T8	8		T12	8		T15	21
auto[SpiFlashAddr3b]	9390	1			T5	4		T8	2		T10	4
auto[SpiFlashAddr4b]	7838	1			T6	4		T8	2		T10	6

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35288

1

T5

4

T8

14

T9

2

auto[1]

26336

1

T6

6

T15

113

T17

90

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32434

1

T6

6

T8

6

T9

2

auto[1]

29190

1

T5

4

T8

8

T10

10

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	41492	1			T6	2		T8	4		T9	2
values[1]	1134	1			T15	3		T17	2		T46	3
values[2]	1533	1			T10	2		T15	6		T17	5
values[3]	1482	1			T10	6		T14	3		T15	3
values[4]	1479	1			T12	4		T17	3		T34	2
values[5]	1495	1			T17	9		T34	2		T50	4
values[6]	1488	1			T17	5		T36	2		T51	4
values[7]	1419	1			T8	6		T15	3		T17	9
values[8]	10102	1			T5	4		T6	4		T8	4

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31175

1

T5

4

T6

6

T8

14

auto[1]

30449

1

T14

3

T17

215

T48

3

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

58334

1

T5

4

T6

6

T8

14

write

3290

1

T12

4

T15

6

T17

14

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19568

1

T5

2

T6

4

T8

6

valids[0x1]

42056

1

T5

2

T6

2

T8

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1592	1			T15	6		T17	6		T36	2
internal_process_ops[0x5a]	1533	1			T8	2		T15	3		T17	4
internal_process_ops[0x05]	22601	1			T8	2		T15	122		T17	80
internal_process_ops[0x35]	1670	1			T15	6		T17	4		T46	3
internal_process_ops[0x15]	1622	1			T6	2		T15	2		T17	8
internal_process_ops[0x03]	1124	1			T8	4		T12	4		T14	1
internal_process_ops[0x0b]	1123	1			T5	2		T14	2		T15	3
internal_process_ops[0x3b]	1105	1			T12	6		T17	4		T34	2
internal_process_ops[0x6b]	1125	1			T8	2		T12	2		T15	5
internal_process_ops[0xbb]	1054	1			T15	1		T17	3		T36	2
internal_process_ops[0xeb]	1095	1			T8	4		T12	4		T15	4

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

60020

1

T5

4

T6

6

T8

14

auto[1]

1604

1

T15

2

T17

8

T46

3

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59180

1

T5

4

T6

6

T8

14

auto[1]

2444

1

T15

5

T17

9

T46

5

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10694

1

T8

2

T9

2

T10

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6553

1

T6

2

T15

88

T46

3

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2107

1

T8

8

T12

4

T15

13

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1774

1

T15

7

T34

4

T46

3

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2578

1

T5

4

T8

2

T10

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2042

1

T15

6

T34

4

T46

11

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1933

1

T8

2

T10

6

T12

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1897

1

T6

4

T15

9

T34

6

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

108

1

T40

2

T30

3

T53

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

88

1

T40

2

T30

3

T53

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

98

1

T46

2

T40

1

T56

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

90

1

T54

2

T30

3

T177

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

121

1

T12

4

T15

1

T75

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

76

1

T40

1

T53

5

T55

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

95

1

T46

1

T30

1

T55

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

113

1

T51

4

T52

6

T30

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

115

1

T36

2

T118

2

T40

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

86

1

T15

2

T30

3

T55

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

87

1

T15

3

T40

2

T30

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

94

1

T30

1

T178

2

T90

5

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

111

1

T53

3

T55

3

T56

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

97

1

T46

1

T40

1

T30

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

101

1

T30

2

T53

2

T56

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

117

1

T46

2

T53

3

T55

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11193

1

T17

84

T43

11

T39

94

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7509

1

T17

47

T43

15

T39

13

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1537

1

T17

10

T48

1

T43

1

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1422

1

T17

6

T43

5

T39

11

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2054

1

T14

2

T17

13

T48

2

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1910

1

T17

13

T43

3

T39

12

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1567

1

T14

1

T17

14

T43

2

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1564

1

T17

14

T43

8

T39

6

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

109

1

T17

2

T73

1

T37

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

110

1

T72

1

T73

1

T76

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

127

1

T17

2

T39

2

T72

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

78

1

T17

4

T39

1

T73

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

79

1

T17

2

T43

1

T76

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

109

1

T39

2

T72

2

T73

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

113

1

T72

1

T74

2

T37

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

93

1

T39

2

T76

1

T89

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

97

1

T74

2

T76

1

T30

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

114

1

T43

1

T76

1

T89

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

115

1

T72

1

T76

1

T30

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

98

1

T17

1

T73

2

T89

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

94

1

T43

1

T73

3

T76

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

111

1

T43

1

T74

2

T76

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

116

1

T72

4

T74

5

T76

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

130

1

T17

3

T39

1

T72

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3826	1			T9	2		T10	2		T15	12
auto[0]	values[0]	valids[0x1]	16274	1			T6	2		T8	4		T12	4
auto[0]	values[1]	valids[0x1]	578	1			T15	3		T46	3		T40	5
auto[0]	values[2]	valids[0x0]	552	1			T10	2		T15	2		T34	4
auto[0]	values[2]	valids[0x1]	329	1			T15	4		T30	3		T53	4
auto[0]	values[3]	valids[0x0]	513	1			T10	6		T15	3		T49	4
auto[0]	values[3]	valids[0x1]	296	1			T40	6		T30	4		T53	3
auto[0]	values[4]	valids[0x0]	546	1			T12	4		T34	2		T49	4
auto[0]	values[4]	valids[0x1]	283	1			T46	1		T40	4		T30	5
auto[0]	values[5]	valids[0x0]	523	1			T34	2		T50	2		T118	2
auto[0]	values[5]	valids[0x1]	285	1			T50	2		T46	1		T40	4
auto[0]	values[6]	valids[0x0]	514	1			T51	2		T40	1		T75	2
auto[0]	values[6]	valids[0x1]	280	1			T36	2		T51	2		T52	2
auto[0]	values[7]	valids[0x0]	522	1			T8	6		T15	3		T118	4
auto[0]	values[7]	valids[0x1]	272	1			T46	2		T30	6		T53	3
auto[0]	values[8]	valids[0x0]	3492	1			T5	2		T6	4		T12	8
auto[0]	values[8]	valids[0x1]	2090	1			T5	2		T8	4		T10	2
auto[1]	values[0]	valids[0x0]	4083	1			T17	25		T43	13		T39	15
auto[1]	values[0]	valids[0x1]	17309	1			T17	127		T43	24		T39	109
auto[1]	values[1]	valids[0x1]	556	1			T17	2		T72	1		T73	2
auto[1]	values[2]	valids[0x0]	391	1			T17	4		T43	1		T39	5
auto[1]	values[2]	valids[0x1]	261	1			T17	1		T43	3		T72	4
auto[1]	values[3]	valids[0x0]	408	1			T17	1		T43	1		T117	3
auto[1]	values[3]	valids[0x1]	265	1			T14	3		T39	2		T72	2
auto[1]	values[4]	valids[0x0]	380	1			T17	2		T43	1		T39	1
auto[1]	values[4]	valids[0x1]	270	1			T17	1		T39	1		T72	1
auto[1]	values[5]	valids[0x0]	419	1			T17	6		T72	4		T74	4
auto[1]	values[5]	valids[0x1]	268	1			T17	3		T72	7		T74	2
auto[1]	values[6]	valids[0x0]	393	1			T17	2		T72	4		T73	4
auto[1]	values[6]	valids[0x1]	301	1			T17	3		T43	3		T39	3
auto[1]	values[7]	valids[0x0]	375	1			T17	6		T117	1		T145	1
auto[1]	values[7]	valids[0x1]	250	1			T17	3		T72	4		T73	1
auto[1]	values[8]	valids[0x0]	2631	1			T17	14		T48	2		T43	4
auto[1]	values[8]	valids[0x1]	1889	1			T17	15		T48	1		T43	3